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vaishnavachathbroonie
vaishnavachath
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broonie
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spi: omap2-mcspi: Revert FIFO support without DMA
MCSPI controller have few limitations regarding the transaction size when the FIFO buffer is enabled and the WCNT feature is used to find the end of word, in this case if WCNT is not a multiple of the FIFO Almost Empty Level (AEL), then the FIFO empty event is not generated correctly. In addition to this limitation, few other unknown sequence of events that causes the FIFO empty status to not reflect the exact status were found when FIFO is being used without DMA enabled during extended testing in AM65x platform. Till the exact root cause is found and fixed, revert the FIFO support without DMA. See J721E Technical Reference Manual (SPRUI1C), section 12.1.5 for further details: http://www.ti.com/lit/pdf/spruil1 This reverts commit 75223bb ("spi: omap2-mcspi: Add FIFO support without DMA") Signed-off-by: Vaishnav Achath <[email protected]> Link: https://msgid.link/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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‎drivers/spi/spi-omap2-mcspi.c

Lines changed: 8 additions & 129 deletions
Original file line numberDiff line numberDiff line change
@@ -53,8 +53,6 @@
5353

5454
/* per-register bitmasks: */
5555
#define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
56-
#define OMAP2_MCSPI_IRQSTATUS_TX0_EMPTY BIT(0)
57-
#define OMAP2_MCSPI_IRQSTATUS_RX0_FULL BIT(2)
5856

5957
#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
6058
#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
@@ -293,7 +291,7 @@ static void omap2_mcspi_set_mode(struct spi_controller *ctlr)
293291
}
294292

295293
static void omap2_mcspi_set_fifo(const struct spi_device *spi,
296-
struct spi_transfer *t, int enable, int dma_enabled)
294+
struct spi_transfer *t, int enable)
297295
{
298296
struct spi_controller *ctlr = spi->controller;
299297
struct omap2_mcspi_cs *cs = spi->controller_state;
@@ -314,28 +312,20 @@ static void omap2_mcspi_set_fifo(const struct spi_device *spi,
314312
max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
315313
else
316314
max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
317-
if (dma_enabled)
318-
wcnt = t->len / bytes_per_word;
319-
else
320-
wcnt = 0;
315+
316+
wcnt = t->len / bytes_per_word;
321317
if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
322318
goto disable_fifo;
323319

324320
xferlevel = wcnt << 16;
325321
if (t->rx_buf != NULL) {
326322
chconf |= OMAP2_MCSPI_CHCONF_FFER;
327-
if (dma_enabled)
328-
xferlevel |= (bytes_per_word - 1) << 8;
329-
else
330-
xferlevel |= (max_fifo_depth - 1) << 8;
323+
xferlevel |= (bytes_per_word - 1) << 8;
331324
}
332325

333326
if (t->tx_buf != NULL) {
334327
chconf |= OMAP2_MCSPI_CHCONF_FFET;
335-
if (dma_enabled)
336-
xferlevel |= bytes_per_word - 1;
337-
else
338-
xferlevel |= (max_fifo_depth - 1);
328+
xferlevel |= bytes_per_word - 1;
339329
}
340330

341331
mcspi_write_reg(ctlr, OMAP2_MCSPI_XFERLEVEL, xferlevel);
@@ -892,113 +882,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
892882
return count - c;
893883
}
894884

895-
static unsigned
896-
omap2_mcspi_txrx_piofifo(struct spi_device *spi, struct spi_transfer *xfer)
897-
{
898-
struct omap2_mcspi_cs *cs = spi->controller_state;
899-
struct omap2_mcspi *mcspi;
900-
unsigned int count, c;
901-
unsigned int iter, cwc;
902-
int last_request;
903-
void __iomem *base = cs->base;
904-
void __iomem *tx_reg;
905-
void __iomem *rx_reg;
906-
void __iomem *chstat_reg;
907-
void __iomem *irqstat_reg;
908-
int word_len, bytes_per_word;
909-
u8 *rx;
910-
const u8 *tx;
911-
912-
mcspi = spi_controller_get_devdata(spi->controller);
913-
count = xfer->len;
914-
c = count;
915-
word_len = cs->word_len;
916-
bytes_per_word = mcspi_bytes_per_word(word_len);
917-
918-
/*
919-
* We store the pre-calculated register addresses on stack to speed
920-
* up the transfer loop.
921-
*/
922-
tx_reg = base + OMAP2_MCSPI_TX0;
923-
rx_reg = base + OMAP2_MCSPI_RX0;
924-
chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
925-
irqstat_reg = base + OMAP2_MCSPI_IRQSTATUS;
926-
927-
if (c < (word_len >> 3))
928-
return 0;
929-
930-
rx = xfer->rx_buf;
931-
tx = xfer->tx_buf;
932-
933-
do {
934-
/* calculate number of words in current iteration */
935-
cwc = min((unsigned int)mcspi->fifo_depth / bytes_per_word,
936-
c / bytes_per_word);
937-
last_request = cwc != (mcspi->fifo_depth / bytes_per_word);
938-
if (tx) {
939-
if (mcspi_wait_for_reg_bit(irqstat_reg,
940-
OMAP2_MCSPI_IRQSTATUS_TX0_EMPTY) < 0) {
941-
dev_err(&spi->dev, "TX Empty timed out\n");
942-
goto out;
943-
}
944-
writel_relaxed(OMAP2_MCSPI_IRQSTATUS_TX0_EMPTY, irqstat_reg);
945-
946-
for (iter = 0; iter < cwc; iter++, tx += bytes_per_word) {
947-
if (bytes_per_word == 1)
948-
writel_relaxed(*tx, tx_reg);
949-
else if (bytes_per_word == 2)
950-
writel_relaxed(*((u16 *)tx), tx_reg);
951-
else if (bytes_per_word == 4)
952-
writel_relaxed(*((u32 *)tx), tx_reg);
953-
}
954-
}
955-
956-
if (rx) {
957-
if (!last_request &&
958-
mcspi_wait_for_reg_bit(irqstat_reg,
959-
OMAP2_MCSPI_IRQSTATUS_RX0_FULL) < 0) {
960-
dev_err(&spi->dev, "RX_FULL timed out\n");
961-
goto out;
962-
}
963-
writel_relaxed(OMAP2_MCSPI_IRQSTATUS_RX0_FULL, irqstat_reg);
964-
965-
for (iter = 0; iter < cwc; iter++, rx += bytes_per_word) {
966-
if (last_request &&
967-
mcspi_wait_for_reg_bit(chstat_reg,
968-
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
969-
dev_err(&spi->dev, "RXS timed out\n");
970-
goto out;
971-
}
972-
if (bytes_per_word == 1)
973-
*rx = readl_relaxed(rx_reg);
974-
else if (bytes_per_word == 2)
975-
*((u16 *)rx) = readl_relaxed(rx_reg);
976-
else if (bytes_per_word == 4)
977-
*((u32 *)rx) = readl_relaxed(rx_reg);
978-
}
979-
}
980-
981-
if (last_request) {
982-
if (mcspi_wait_for_reg_bit(chstat_reg,
983-
OMAP2_MCSPI_CHSTAT_EOT) < 0) {
984-
dev_err(&spi->dev, "EOT timed out\n");
985-
goto out;
986-
}
987-
if (mcspi_wait_for_reg_bit(chstat_reg,
988-
OMAP2_MCSPI_CHSTAT_TXFFE) < 0) {
989-
dev_err(&spi->dev, "TXFFE timed out\n");
990-
goto out;
991-
}
992-
omap2_mcspi_set_enable(spi, 0);
993-
}
994-
c -= cwc * bytes_per_word;
995-
} while (c >= bytes_per_word);
996-
997-
out:
998-
omap2_mcspi_set_enable(spi, 1);
999-
return count - c;
1000-
}
1001-
1002885
static u32 omap2_mcspi_calc_divisor(u32 speed_hz, u32 ref_clk_hz)
1003886
{
1004887
u32 div;
@@ -1323,9 +1206,7 @@ static int omap2_mcspi_transfer_one(struct spi_controller *ctlr,
13231206
if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
13241207
ctlr->cur_msg_mapped &&
13251208
ctlr->can_dma(ctlr, spi, t))
1326-
omap2_mcspi_set_fifo(spi, t, 1, 1);
1327-
else if (t->len > OMAP2_MCSPI_MAX_FIFODEPTH)
1328-
omap2_mcspi_set_fifo(spi, t, 1, 0);
1209+
omap2_mcspi_set_fifo(spi, t, 1);
13291210

13301211
omap2_mcspi_set_enable(spi, 1);
13311212

@@ -1338,8 +1219,6 @@ static int omap2_mcspi_transfer_one(struct spi_controller *ctlr,
13381219
ctlr->cur_msg_mapped &&
13391220
ctlr->can_dma(ctlr, spi, t))
13401221
count = omap2_mcspi_txrx_dma(spi, t);
1341-
else if (mcspi->fifo_depth > 0)
1342-
count = omap2_mcspi_txrx_piofifo(spi, t);
13431222
else
13441223
count = omap2_mcspi_txrx_pio(spi, t);
13451224

@@ -1352,7 +1231,7 @@ static int omap2_mcspi_transfer_one(struct spi_controller *ctlr,
13521231
omap2_mcspi_set_enable(spi, 0);
13531232

13541233
if (mcspi->fifo_depth > 0)
1355-
omap2_mcspi_set_fifo(spi, t, 0, 0);
1234+
omap2_mcspi_set_fifo(spi, t, 0);
13561235

13571236
out:
13581237
/* Restore defaults if they were overriden */
@@ -1375,7 +1254,7 @@ static int omap2_mcspi_transfer_one(struct spi_controller *ctlr,
13751254
omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
13761255

13771256
if (mcspi->fifo_depth > 0 && t)
1378-
omap2_mcspi_set_fifo(spi, t, 0, 0);
1257+
omap2_mcspi_set_fifo(spi, t, 0);
13791258

13801259
return status;
13811260
}

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