@@ -1108,76 +1108,6 @@ mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
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mlxsw_reg_sfgc_mid_set (payload , MLXSW_PORT_MID );
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}
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- /* SFTR - Switch Flooding Table Register
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- * -------------------------------------
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- * The switch flooding table is used for flooding packet replication. The table
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- * defines a bit mask of ports for packet replication.
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- */
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- #define MLXSW_REG_SFTR_ID 0x2012
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- #define MLXSW_REG_SFTR_LEN 0x420
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-
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- MLXSW_REG_DEFINE (sftr , MLXSW_REG_SFTR_ID , MLXSW_REG_SFTR_LEN );
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-
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- /* reg_sftr_swid
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- * Switch partition ID with which to associate the port.
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- * Access: Index
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- */
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- MLXSW_ITEM32 (reg , sftr , swid , 0x00 , 24 , 8 );
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-
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- /* reg_sftr_flood_table
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- * Flooding table index to associate with the specific type on the specific
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- * switch partition.
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- * Access: Index
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- */
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- MLXSW_ITEM32 (reg , sftr , flood_table , 0x00 , 16 , 6 );
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-
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- /* reg_sftr_index
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- * Index. Used as an index into the Flooding Table in case the table is
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- * configured to use VID / FID or FID Offset.
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- * Access: Index
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- */
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- MLXSW_ITEM32 (reg , sftr , index , 0x00 , 0 , 16 );
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-
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- /* reg_sftr_table_type
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- * See mlxsw_flood_table_type
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- * Access: RW
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- */
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- MLXSW_ITEM32 (reg , sftr , table_type , 0x04 , 16 , 3 );
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-
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- /* reg_sftr_range
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- * Range of entries to update
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- * Access: Index
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- */
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- MLXSW_ITEM32 (reg , sftr , range , 0x04 , 0 , 16 );
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-
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- /* reg_sftr_port
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- * Local port membership (1 bit per port).
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- * Access: RW
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- */
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- MLXSW_ITEM_BIT_ARRAY (reg , sftr , port , 0x20 , 0x20 , 1 );
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-
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- /* reg_sftr_cpu_port_mask
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- * CPU port mask (1 bit per port).
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- * Access: W
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- */
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- MLXSW_ITEM_BIT_ARRAY (reg , sftr , port_mask , 0x220 , 0x20 , 1 );
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-
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- static inline void mlxsw_reg_sftr_pack (char * payload ,
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- unsigned int flood_table ,
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- unsigned int index ,
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- enum mlxsw_flood_table_type table_type ,
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- unsigned int range , u8 port , bool set )
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- {
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- MLXSW_REG_ZERO (sftr , payload );
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- mlxsw_reg_sftr_swid_set (payload , 0 );
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- mlxsw_reg_sftr_flood_table_set (payload , flood_table );
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- mlxsw_reg_sftr_index_set (payload , index );
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- mlxsw_reg_sftr_table_type_set (payload , table_type );
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- mlxsw_reg_sftr_range_set (payload , range );
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- mlxsw_reg_sftr_port_set (payload , port , set );
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- mlxsw_reg_sftr_port_mask_set (payload , port , 1 );
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- }
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-
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/* SFDF - Switch Filtering DB Flush
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* --------------------------------
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* The switch filtering DB flush register is used to flush the FDB.
@@ -2105,6 +2035,76 @@ static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port,
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mlxsw_reg_spevet_et_vlan_set (payload , et_vlan );
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}
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+ /* SFTR-V2 - Switch Flooding Table Version 2 Register
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+ * --------------------------------------------------
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+ * The switch flooding table is used for flooding packet replication. The table
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+ * defines a bit mask of ports for packet replication.
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+ */
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+ #define MLXSW_REG_SFTR2_ID 0x202F
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+ #define MLXSW_REG_SFTR2_LEN 0x120
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+
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+ MLXSW_REG_DEFINE (sftr2 , MLXSW_REG_SFTR2_ID , MLXSW_REG_SFTR2_LEN );
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+
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+ /* reg_sftr2_swid
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+ * Switch partition ID with which to associate the port.
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+ * Access: Index
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+ */
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+ MLXSW_ITEM32 (reg , sftr2 , swid , 0x00 , 24 , 8 );
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+
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+ /* reg_sftr2_flood_table
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+ * Flooding table index to associate with the specific type on the specific
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+ * switch partition.
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+ * Access: Index
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+ */
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+ MLXSW_ITEM32 (reg , sftr2 , flood_table , 0x00 , 16 , 6 );
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+
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+ /* reg_sftr2_index
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+ * Index. Used as an index into the Flooding Table in case the table is
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+ * configured to use VID / FID or FID Offset.
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+ * Access: Index
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+ */
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+ MLXSW_ITEM32 (reg , sftr2 , index , 0x00 , 0 , 16 );
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+
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+ /* reg_sftr2_table_type
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+ * See mlxsw_flood_table_type
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+ * Access: RW
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+ */
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+ MLXSW_ITEM32 (reg , sftr2 , table_type , 0x04 , 16 , 3 );
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+
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+ /* reg_sftr2_range
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+ * Range of entries to update
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+ * Access: Index
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+ */
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+ MLXSW_ITEM32 (reg , sftr2 , range , 0x04 , 0 , 16 );
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+
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+ /* reg_sftr2_port
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+ * Local port membership (1 bit per port).
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+ * Access: RW
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+ */
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+ MLXSW_ITEM_BIT_ARRAY (reg , sftr2 , port , 0x20 , 0x80 , 1 );
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+
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+ /* reg_sftr2_port_mask
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+ * Local port mask (1 bit per port).
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+ * Access: WO
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+ */
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+ MLXSW_ITEM_BIT_ARRAY (reg , sftr2 , port_mask , 0xA0 , 0x80 , 1 );
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+
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+ static inline void mlxsw_reg_sftr2_pack (char * payload ,
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+ unsigned int flood_table ,
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+ unsigned int index ,
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+ enum mlxsw_flood_table_type table_type ,
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+ unsigned int range , u16 port , bool set )
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+ {
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+ MLXSW_REG_ZERO (sftr2 , payload );
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+ mlxsw_reg_sftr2_swid_set (payload , 0 );
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+ mlxsw_reg_sftr2_flood_table_set (payload , flood_table );
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+ mlxsw_reg_sftr2_index_set (payload , index );
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+ mlxsw_reg_sftr2_table_type_set (payload , table_type );
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+ mlxsw_reg_sftr2_range_set (payload , range );
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+ mlxsw_reg_sftr2_port_set (payload , port , set );
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+ mlxsw_reg_sftr2_port_mask_set (payload , port , 1 );
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+ }
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+
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/* CWTP - Congetion WRED ECN TClass Profile
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* ----------------------------------------
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* Configures the profiles for queues of egress port and traffic class
@@ -12383,7 +12383,6 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG (spvm ),
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MLXSW_REG (spaft ),
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MLXSW_REG (sfgc ),
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- MLXSW_REG (sftr ),
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MLXSW_REG (sfdf ),
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MLXSW_REG (sldr ),
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MLXSW_REG (slcr ),
@@ -12396,6 +12395,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG (spvmlr ),
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MLXSW_REG (spvc ),
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MLXSW_REG (spevet ),
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+ MLXSW_REG (sftr2 ),
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MLXSW_REG (cwtp ),
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MLXSW_REG (cwtpm ),
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MLXSW_REG (pgcr ),
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