@@ -30,6 +30,26 @@ static const char * const pin_type_name[] = {
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[ICE_DPLL_PIN_TYPE_RCLK_INPUT ] = "rclk-input" ,
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};
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+ /**
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+ * ice_dpll_is_reset - check if reset is in progress
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+ * @pf: private board structure
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+ * @extack: error reporting
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+ *
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+ * If reset is in progress, fill extack with error.
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+ *
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+ * Return:
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+ * * false - no reset in progress
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+ * * true - reset in progress
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+ */
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+ static bool ice_dpll_is_reset (struct ice_pf * pf , struct netlink_ext_ack * extack )
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+ {
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+ if (ice_is_reset_in_progress (pf -> state )) {
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+ NL_SET_ERR_MSG (extack , "PF reset in progress" );
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+ return true;
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+ }
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+ return false;
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+ }
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+
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/**
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* ice_dpll_pin_freq_set - set pin's frequency
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* @pf: private board structure
@@ -109,6 +129,9 @@ ice_dpll_frequency_set(const struct dpll_pin *pin, void *pin_priv,
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struct ice_pf * pf = d -> pf ;
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int ret ;
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+ if (ice_dpll_is_reset (pf , extack ))
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+ return - EBUSY ;
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+
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mutex_lock (& pf -> dplls .lock );
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ret = ice_dpll_pin_freq_set (pf , p , pin_type , frequency , extack );
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mutex_unlock (& pf -> dplls .lock );
@@ -254,6 +277,7 @@ ice_dpll_output_frequency_get(const struct dpll_pin *pin, void *pin_priv,
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* ice_dpll_pin_enable - enable a pin on dplls
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* @hw: board private hw structure
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* @pin: pointer to a pin
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+ * @dpll_idx: dpll index to connect to output pin
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* @pin_type: type of pin being enabled
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* @extack: error reporting
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*
@@ -266,7 +290,7 @@ ice_dpll_output_frequency_get(const struct dpll_pin *pin, void *pin_priv,
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*/
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static int
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ice_dpll_pin_enable (struct ice_hw * hw , struct ice_dpll_pin * pin ,
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- enum ice_dpll_pin_type pin_type ,
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+ u8 dpll_idx , enum ice_dpll_pin_type pin_type ,
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struct netlink_ext_ack * extack )
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{
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u8 flags = 0 ;
@@ -280,10 +304,12 @@ ice_dpll_pin_enable(struct ice_hw *hw, struct ice_dpll_pin *pin,
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ret = ice_aq_set_input_pin_cfg (hw , pin -> idx , 0 , flags , 0 , 0 );
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break ;
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case ICE_DPLL_PIN_TYPE_OUTPUT :
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+ flags = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL ;
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if (pin -> flags [0 ] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN )
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flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN ;
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flags |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN ;
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- ret = ice_aq_set_output_pin_cfg (hw , pin -> idx , flags , 0 , 0 , 0 );
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+ ret = ice_aq_set_output_pin_cfg (hw , pin -> idx , flags , dpll_idx ,
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+ 0 , 0 );
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break ;
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default :
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return - EINVAL ;
@@ -370,7 +396,7 @@ ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
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case ICE_DPLL_PIN_TYPE_INPUT :
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ret = ice_aq_get_input_pin_cfg (& pf -> hw , pin -> idx , NULL , NULL ,
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NULL , & pin -> flags [0 ],
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- & pin -> freq , NULL );
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+ & pin -> freq , & pin -> phase_adjust );
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if (ret )
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goto err ;
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if (ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN & pin -> flags [0 ]) {
@@ -398,14 +424,27 @@ ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
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break ;
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case ICE_DPLL_PIN_TYPE_OUTPUT :
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ret = ice_aq_get_output_pin_cfg (& pf -> hw , pin -> idx ,
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- & pin -> flags [0 ], NULL ,
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+ & pin -> flags [0 ], & parent ,
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& pin -> freq , NULL );
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if (ret )
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goto err ;
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- if (ICE_AQC_SET_CGU_OUT_CFG_OUT_EN & pin -> flags [0 ])
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- pin -> state [0 ] = DPLL_PIN_STATE_CONNECTED ;
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- else
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- pin -> state [0 ] = DPLL_PIN_STATE_DISCONNECTED ;
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+
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+ parent &= ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL ;
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+ if (ICE_AQC_SET_CGU_OUT_CFG_OUT_EN & pin -> flags [0 ]) {
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+ pin -> state [pf -> dplls .eec .dpll_idx ] =
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+ parent == pf -> dplls .eec .dpll_idx ?
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+ DPLL_PIN_STATE_CONNECTED :
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+ DPLL_PIN_STATE_DISCONNECTED ;
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+ pin -> state [pf -> dplls .pps .dpll_idx ] =
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+ parent == pf -> dplls .pps .dpll_idx ?
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+ DPLL_PIN_STATE_CONNECTED :
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+ DPLL_PIN_STATE_DISCONNECTED ;
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+ } else {
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+ pin -> state [pf -> dplls .eec .dpll_idx ] =
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+ DPLL_PIN_STATE_DISCONNECTED ;
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+ pin -> state [pf -> dplls .pps .dpll_idx ] =
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+ DPLL_PIN_STATE_DISCONNECTED ;
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+ }
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break ;
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case ICE_DPLL_PIN_TYPE_RCLK_INPUT :
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for (parent = 0 ; parent < pf -> dplls .rclk .num_parents ;
@@ -568,9 +607,13 @@ ice_dpll_pin_state_set(const struct dpll_pin *pin, void *pin_priv,
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struct ice_pf * pf = d -> pf ;
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int ret ;
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+ if (ice_dpll_is_reset (pf , extack ))
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+ return - EBUSY ;
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+
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mutex_lock (& pf -> dplls .lock );
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if (enable )
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- ret = ice_dpll_pin_enable (& pf -> hw , p , pin_type , extack );
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+ ret = ice_dpll_pin_enable (& pf -> hw , p , d -> dpll_idx , pin_type ,
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+ extack );
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else
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ret = ice_dpll_pin_disable (& pf -> hw , p , pin_type , extack );
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if (!ret )
@@ -603,6 +646,11 @@ ice_dpll_output_state_set(const struct dpll_pin *pin, void *pin_priv,
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struct netlink_ext_ack * extack )
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{
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bool enable = state == DPLL_PIN_STATE_CONNECTED ;
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+ struct ice_dpll_pin * p = pin_priv ;
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+ struct ice_dpll * d = dpll_priv ;
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+
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+ if (!enable && p -> state [d -> dpll_idx ] == DPLL_PIN_STATE_DISCONNECTED )
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+ return 0 ;
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return ice_dpll_pin_state_set (pin , pin_priv , dpll , dpll_priv , enable ,
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extack , ICE_DPLL_PIN_TYPE_OUTPUT );
@@ -665,14 +713,16 @@ ice_dpll_pin_state_get(const struct dpll_pin *pin, void *pin_priv,
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struct ice_pf * pf = d -> pf ;
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int ret ;
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+ if (ice_dpll_is_reset (pf , extack ))
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+ return - EBUSY ;
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+
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mutex_lock (& pf -> dplls .lock );
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ret = ice_dpll_pin_state_update (pf , p , pin_type , extack );
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if (ret )
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goto unlock ;
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- if (pin_type == ICE_DPLL_PIN_TYPE_INPUT )
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+ if (pin_type == ICE_DPLL_PIN_TYPE_INPUT ||
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+ pin_type == ICE_DPLL_PIN_TYPE_OUTPUT )
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* state = p -> state [d -> dpll_idx ];
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- else if (pin_type == ICE_DPLL_PIN_TYPE_OUTPUT )
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- * state = p -> state [0 ];
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ret = 0 ;
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unlock :
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mutex_unlock (& pf -> dplls .lock );
@@ -790,6 +840,9 @@ ice_dpll_input_prio_set(const struct dpll_pin *pin, void *pin_priv,
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struct ice_pf * pf = d -> pf ;
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int ret ;
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+ if (ice_dpll_is_reset (pf , extack ))
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+ return - EBUSY ;
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+
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mutex_lock (& pf -> dplls .lock );
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ret = ice_dpll_hw_input_prio_set (pf , d , p , prio , extack );
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mutex_unlock (& pf -> dplls .lock );
@@ -910,6 +963,9 @@ ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
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u8 flag , flags_en = 0 ;
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int ret ;
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+ if (ice_dpll_is_reset (pf , extack ))
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+ return - EBUSY ;
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+
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mutex_lock (& pf -> dplls .lock );
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switch (type ) {
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case ICE_DPLL_PIN_TYPE_INPUT :
@@ -1069,6 +1125,9 @@ ice_dpll_rclk_state_on_pin_set(const struct dpll_pin *pin, void *pin_priv,
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int ret = - EINVAL ;
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u32 hw_idx ;
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+ if (ice_dpll_is_reset (pf , extack ))
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+ return - EBUSY ;
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+
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mutex_lock (& pf -> dplls .lock );
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hw_idx = parent -> idx - pf -> dplls .base_rclk_idx ;
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if (hw_idx >= pf -> dplls .num_inputs )
@@ -1123,6 +1182,9 @@ ice_dpll_rclk_state_on_pin_get(const struct dpll_pin *pin, void *pin_priv,
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int ret = - EINVAL ;
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u32 hw_idx ;
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+ if (ice_dpll_is_reset (pf , extack ))
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+ return - EBUSY ;
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+
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mutex_lock (& pf -> dplls .lock );
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hw_idx = parent -> idx - pf -> dplls .base_rclk_idx ;
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if (hw_idx >= pf -> dplls .num_inputs )
@@ -1305,8 +1367,10 @@ static void ice_dpll_periodic_work(struct kthread_work *work)
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struct ice_pf * pf = container_of (d , struct ice_pf , dplls );
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struct ice_dpll * de = & pf -> dplls .eec ;
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struct ice_dpll * dp = & pf -> dplls .pps ;
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- int ret ;
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+ int ret = 0 ;
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+ if (ice_is_reset_in_progress (pf -> state ))
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+ goto resched ;
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mutex_lock (& pf -> dplls .lock );
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ret = ice_dpll_update_state (pf , de , false);
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if (!ret )
@@ -1326,6 +1390,7 @@ static void ice_dpll_periodic_work(struct kthread_work *work)
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ice_dpll_notify_changes (de );
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ice_dpll_notify_changes (dp );
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+ resched :
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/* Run twice a second or reschedule if update failed */
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kthread_queue_delayed_work (d -> kworker , & d -> work ,
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ret ? msecs_to_jiffies (10 ) :
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