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45 | 45 | * Contact Information:
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46 | 46 |
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47 | 47 | */
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48 |
| -#include <linux/ntb.h> |
| 48 | +#include <linux/ntb_transport.h> |
49 | 49 |
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| 50 | +#define NTB_LINK_STATUS_ACTIVE 0x2000 |
| 51 | +#define NTB_LINK_SPEED_MASK 0x000f |
| 52 | +#define NTB_LINK_WIDTH_MASK 0x03f0 |
| 53 | + |
| 54 | +#define SNB_MSIX_CNT 4 |
| 55 | +#define SNB_MAX_B2B_SPADS 16 |
| 56 | +#define SNB_MAX_COMPAT_SPADS 16 |
| 57 | +/* Reserve the uppermost bit for link interrupt */ |
| 58 | +#define SNB_MAX_DB_BITS 15 |
| 59 | +#define SNB_LINK_DB 15 |
| 60 | +#define SNB_DB_BITS_PER_VEC 5 |
| 61 | +#define HSX_SPLITBAR_MAX_MW 3 |
| 62 | +#define SNB_MAX_MW 2 |
| 63 | +#define SNB_ERRATA_MAX_MW 1 |
| 64 | + |
| 65 | +#define SNB_DB_HW_LINK 0x8000 |
| 66 | + |
| 67 | +#define SNB_UNCERRSTS_OFFSET 0x014C |
| 68 | +#define SNB_CORERRSTS_OFFSET 0x0158 |
| 69 | +#define SNB_LINK_STATUS_OFFSET 0x01A2 |
| 70 | +#define SNB_PCICMD_OFFSET 0x0504 |
| 71 | +#define SNB_DEVCTRL_OFFSET 0x0598 |
| 72 | +#define SNB_DEVSTS_OFFSET 0x059A |
| 73 | +#define SNB_SLINK_STATUS_OFFSET 0x05A2 |
| 74 | + |
| 75 | +#define SNB_PBAR2LMT_OFFSET 0x0000 |
| 76 | +#define SNB_PBAR4LMT_OFFSET 0x0008 |
| 77 | +#define SNB_PBAR5LMT_OFFSET 0x000C |
| 78 | +#define SNB_PBAR2XLAT_OFFSET 0x0010 |
| 79 | +#define SNB_PBAR4XLAT_OFFSET 0x0018 |
| 80 | +#define SNB_PBAR5XLAT_OFFSET 0x001C |
| 81 | +#define SNB_SBAR2LMT_OFFSET 0x0020 |
| 82 | +#define SNB_SBAR4LMT_OFFSET 0x0028 |
| 83 | +#define SNB_SBAR5LMT_OFFSET 0x002C |
| 84 | +#define SNB_SBAR2XLAT_OFFSET 0x0030 |
| 85 | +#define SNB_SBAR4XLAT_OFFSET 0x0038 |
| 86 | +#define SNB_SBAR5XLAT_OFFSET 0x003C |
| 87 | +#define SNB_SBAR0BASE_OFFSET 0x0040 |
| 88 | +#define SNB_SBAR2BASE_OFFSET 0x0048 |
| 89 | +#define SNB_SBAR4BASE_OFFSET 0x0050 |
| 90 | +#define SNB_SBAR5BASE_OFFSET 0x0054 |
| 91 | +#define SNB_NTBCNTL_OFFSET 0x0058 |
| 92 | +#define SNB_SBDF_OFFSET 0x005C |
| 93 | +#define SNB_PDOORBELL_OFFSET 0x0060 |
| 94 | +#define SNB_PDBMSK_OFFSET 0x0062 |
| 95 | +#define SNB_SDOORBELL_OFFSET 0x0064 |
| 96 | +#define SNB_SDBMSK_OFFSET 0x0066 |
| 97 | +#define SNB_USMEMMISS_OFFSET 0x0070 |
| 98 | +#define SNB_SPAD_OFFSET 0x0080 |
| 99 | +#define SNB_SPADSEMA4_OFFSET 0x00c0 |
| 100 | +#define SNB_WCCNTRL_OFFSET 0x00e0 |
| 101 | +#define SNB_B2B_SPAD_OFFSET 0x0100 |
| 102 | +#define SNB_B2B_DOORBELL_OFFSET 0x0140 |
| 103 | +#define SNB_B2B_XLAT_OFFSETL 0x0144 |
| 104 | +#define SNB_B2B_XLAT_OFFSETU 0x0148 |
| 105 | + |
| 106 | +/* |
| 107 | + * The addresses are setup so the 32bit BARs can function. Thus |
| 108 | + * the addresses are all in 32bit space |
| 109 | + */ |
| 110 | +#define SNB_MBAR01_USD_ADDR 0x000000002100000CULL |
| 111 | +#define SNB_MBAR23_USD_ADDR 0x000000004100000CULL |
| 112 | +#define SNB_MBAR4_USD_ADDR 0x000000008100000CULL |
| 113 | +#define SNB_MBAR5_USD_ADDR 0x00000000A100000CULL |
| 114 | +#define SNB_MBAR01_DSD_ADDR 0x000000002000000CULL |
| 115 | +#define SNB_MBAR23_DSD_ADDR 0x000000004000000CULL |
| 116 | +#define SNB_MBAR4_DSD_ADDR 0x000000008000000CULL |
| 117 | +#define SNB_MBAR5_DSD_ADDR 0x00000000A000000CULL |
| 118 | + |
| 119 | +#define BWD_MSIX_CNT 34 |
| 120 | +#define BWD_MAX_SPADS 16 |
| 121 | +#define BWD_MAX_DB_BITS 34 |
| 122 | +#define BWD_DB_BITS_PER_VEC 1 |
| 123 | +#define BWD_MAX_MW 2 |
| 124 | + |
| 125 | +#define BWD_PCICMD_OFFSET 0xb004 |
| 126 | +#define BWD_MBAR23_OFFSET 0xb018 |
| 127 | +#define BWD_MBAR45_OFFSET 0xb020 |
| 128 | +#define BWD_DEVCTRL_OFFSET 0xb048 |
| 129 | +#define BWD_LINK_STATUS_OFFSET 0xb052 |
| 130 | +#define BWD_ERRCORSTS_OFFSET 0xb110 |
| 131 | + |
| 132 | +#define BWD_SBAR2XLAT_OFFSET 0x0008 |
| 133 | +#define BWD_SBAR4XLAT_OFFSET 0x0010 |
| 134 | +#define BWD_PDOORBELL_OFFSET 0x0020 |
| 135 | +#define BWD_PDBMSK_OFFSET 0x0028 |
| 136 | +#define BWD_NTBCNTL_OFFSET 0x0060 |
| 137 | +#define BWD_EBDF_OFFSET 0x0064 |
| 138 | +#define BWD_SPAD_OFFSET 0x0080 |
| 139 | +#define BWD_SPADSEMA_OFFSET 0x00c0 |
| 140 | +#define BWD_STKYSPAD_OFFSET 0x00c4 |
| 141 | +#define BWD_PBAR2XLAT_OFFSET 0x8008 |
| 142 | +#define BWD_PBAR4XLAT_OFFSET 0x8010 |
| 143 | +#define BWD_B2B_DOORBELL_OFFSET 0x8020 |
| 144 | +#define BWD_B2B_SPAD_OFFSET 0x8080 |
| 145 | +#define BWD_B2B_SPADSEMA_OFFSET 0x80c0 |
| 146 | +#define BWD_B2B_STKYSPAD_OFFSET 0x80c4 |
| 147 | + |
| 148 | +#define BWD_MODPHY_PCSREG4 0x1c004 |
| 149 | +#define BWD_MODPHY_PCSREG6 0x1c006 |
| 150 | + |
| 151 | +#define BWD_IP_BASE 0xC000 |
| 152 | +#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024) |
| 153 | +#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180) |
| 154 | +#define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040) |
| 155 | +#define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324) |
| 156 | + |
| 157 | +#define BWD_DESKEWSTS_DBERR (1 << 15) |
| 158 | +#define BWD_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20) |
| 159 | +#define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2) |
| 160 | +#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF |
| 161 | + |
| 162 | +#define NTB_CNTL_CFG_LOCK (1 << 0) |
| 163 | +#define NTB_CNTL_LINK_DISABLE (1 << 1) |
| 164 | +#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2) |
| 165 | +#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4) |
| 166 | +#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6) |
| 167 | +#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8) |
| 168 | +#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12) |
| 169 | +#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14) |
| 170 | +#define BWD_CNTL_LINK_DOWN (1 << 16) |
| 171 | + |
| 172 | +#define NTB_PPD_OFFSET 0x00D4 |
| 173 | +#define SNB_PPD_CONN_TYPE 0x0003 |
| 174 | +#define SNB_PPD_DEV_TYPE 0x0010 |
| 175 | +#define SNB_PPD_SPLIT_BAR (1 << 6) |
| 176 | +#define BWD_PPD_INIT_LINK 0x0008 |
| 177 | +#define BWD_PPD_CONN_TYPE 0x0300 |
| 178 | +#define BWD_PPD_DEV_TYPE 0x1000 |
50 | 179 | #define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
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51 | 180 | #define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
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52 | 181 | #define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
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