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perf vendor events: Add JSON metrics for Cascadelake server
Add JSON metrics (based on event list v1) for Cascadelake server Signed-off-by: Kan Liang <[email protected]> Acked-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
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‎tools/perf/pmu-events/arch/x86/cascadelakex/cache.json

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‎tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json

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[
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{
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"BriefDescription": "Instructions Per Cycle (per logical thread)",
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"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
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"MetricGroup": "TopDownL1",
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"MetricName": "IPC"
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},
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{
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"BriefDescription": "Uops Per Instruction",
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"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
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"MetricGroup": "Pipeline",
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"MetricName": "UPI"
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},
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{
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"BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely consumed by program instructions",
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"MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ((UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 64 * ( ICACHE_64B.IFTAG_HIT + ICACHE_64B.IFTAG_MISS ) / 4.1) )",
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"MetricGroup": "Frontend",
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"MetricName": "IFetch_Line_Utilization"
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},
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{
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"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache)",
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"MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )",
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"MetricGroup": "DSB; Frontend_Bandwidth",
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"MetricName": "DSB_Coverage"
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},
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{
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"BriefDescription": "Cycles Per Instruction (threaded)",
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"MetricExpr": "1 / (INST_RETIRED.ANY / cycles)",
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"MetricGroup": "Pipeline;Summary",
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"MetricName": "CPI"
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},
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{
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"BriefDescription": "Per-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTune.",
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"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
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"MetricGroup": "Summary",
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"MetricName": "CLKS"
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},
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{
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"BriefDescription": "Total issue-pipeline slots",
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"MetricExpr": "4*(( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles)",
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"MetricGroup": "TopDownL1",
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"MetricName": "SLOTS"
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},
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{
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"BriefDescription": "Total number of retired Instructions",
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"MetricExpr": "INST_RETIRED.ANY",
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"MetricGroup": "Summary",
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"MetricName": "Instructions"
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},
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{
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"BriefDescription": "Instructions Per Cycle (per physical core)",
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"MetricExpr": "INST_RETIRED.ANY / (( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles)",
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"MetricGroup": "SMT",
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"MetricName": "CoreIPC"
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},
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{
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"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
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"MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
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"MetricGroup": "Pipeline;Ports_Utilization",
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"MetricName": "ILP"
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},
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{
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"BriefDescription": "Average Branch Address Clear Cost (fraction of cycles)",
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"MetricExpr": "2* (( RS_EVENTS.EMPTY_CYCLES - ICACHE_16B.IFDATA_STALL - ICACHE_64B.IFTAG_STALL ) / RS_EVENTS.EMPTY_END)",
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"MetricGroup": "Unknown_Branches",
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"MetricName": "BAClear_Cost"
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},
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{
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"BriefDescription": "Core actual clocks when any thread is active on the physical core",
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"MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD",
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"MetricGroup": "SMT",
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"MetricName": "CORE_CLKS"
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},
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{
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"BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads",
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"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS_PS + MEM_LOAD_RETIRED.FB_HIT_PS )",
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"MetricGroup": "Memory_Bound;Memory_Lat",
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"MetricName": "Load_Miss_Real_Latency"
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},
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{
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"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss)",
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"MetricExpr": "L1D_PEND_MISS.PENDING / (( L1D_PEND_MISS.PENDING_CYCLES_ANY / 2) if #SMT_on else L1D_PEND_MISS.PENDING_CYCLES)",
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"MetricGroup": "Memory_Bound;Memory_BW",
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"MetricName": "MLP"
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},
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{
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"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
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"MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * (( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles) )",
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"MetricGroup": "TLB",
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"MetricName": "Page_Walks_Utilization"
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},
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{
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"BriefDescription": "Average CPU Utilization",
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"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
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"MetricGroup": "Summary",
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"MetricName": "CPU_Utilization"
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},
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{
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"BriefDescription": "Giga Floating Point Operations Per Second",
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"MetricExpr": "(( 1*( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2* FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4*( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8* FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / 1000000000 / duration_time",
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"MetricGroup": "FLOPS;Summary",
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"MetricName": "GFLOPs"
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},
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{
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"BriefDescription": "Average Frequency Utilization relative nominal frequency",
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"MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC",
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"MetricGroup": "Power",
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"MetricName": "Turbo_Utilization"
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},
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{
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"BriefDescription": "Fraction of cycles where both hardware threads were active",
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"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
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"MetricGroup": "SMT;Summary",
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"MetricName": "SMT_2T_Utilization"
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},
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{
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"BriefDescription": "Fraction of cycles spent in Kernel mode",
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"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC:u / CPU_CLK_UNHALTED.REF_TSC",
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"MetricGroup": "Summary",
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"MetricName": "Kernel_Utilization"
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},
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{
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"BriefDescription": "C3 residency percent per core",
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"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C3_Core_Residency"
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},
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{
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"BriefDescription": "C6 residency percent per core",
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"MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C6_Core_Residency"
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},
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{
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"BriefDescription": "C7 residency percent per core",
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"MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C7_Core_Residency"
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},
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{
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"BriefDescription": "C2 residency percent per package",
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"MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C2_Pkg_Residency"
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},
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{
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"BriefDescription": "C3 residency percent per package",
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"MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C3_Pkg_Residency"
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},
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{
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"BriefDescription": "C6 residency percent per package",
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"MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C6_Pkg_Residency"
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},
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{
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"BriefDescription": "C7 residency percent per package",
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"MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C7_Pkg_Residency"
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}
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]

‎tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json

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[
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{
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"EventCode": "0xC7",
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"UMask": "0x1",
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"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x2",
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"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x4",
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x8",
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x10",
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"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x20",
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"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x40",
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"BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x80",
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"BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xCA",
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"UMask": "0x1e",
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"BriefDescription": "Cycles with any input/output SSE or FP assist",
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"Counter": "0,1,2,3",
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"EventName": "FP_ASSIST.ANY",
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"CounterMask": "1",
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"PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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}
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]

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