RDMA/mlx5: Set MR cache limit for both PF and VF

MR cache limit is used for PF but not set for VF causing better latency
on the PF. Issue is also in upstream and not limited to UEK.

This change is not upstream and Mellanox cannot commit at this time it
will be accepted upstream.

Orabug: 31358080

Signed-off-by: Nikhil Krishna <[email protected]>
Tested-by: Ria Mirchandani <[email protected]>
Signed-off-by: Qing Huang <[email protected]>
Reviewed-by: Håkon Bugge <[email protected]>

Author: Nikhil Krishna

drivers/infiniband/hw/mlx5/mr.c

@@ -643,12 +643,16 @@ int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
 		ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) /
 			   MLX5_IB_UMR_OCTOWORD;
 		ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
+#ifdef WITHOUT_ORACLE_EXTENSIONS
 		if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) &&
 		    !dev->is_rep &&
 		    mlx5_core_is_pf(dev->mdev))
 			ent->limit = dev->mdev->profile->mr_cache[i].limit;
 		else
 			ent->limit = 0;
+#else
+		ent->limit = dev->mdev->profile->mr_cache[i].limit;
+#endif /* WITHOUT_ORACLE_EXTENSIONS */
 		queue_work(cache->wq, &ent->work);
 	}