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agd5fairlied
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radeon: fix PCI bus mastering support enables.
Someone noticed these registers moved around for later chips, so we redo the codepaths per-chip. PCIE chips don't appear to require explicit enables. Signed-off-by: Dave Airlie <[email protected]>
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+61
-24
lines changed

3 files changed

+61
-24
lines changed

drivers/gpu/drm/radeon/radeon_cp.c

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -363,6 +363,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
363363
R300_cp_microcode[i][0]);
364364
}
365365
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
366+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
366367
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
367368
DRM_INFO("Loading R400 Microcode\n");
368369
for (i = 0; i < 256; i++) {
@@ -652,8 +653,18 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
652653
RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
653654

654655
/* Turn on bus mastering */
655-
tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
656-
RADEON_WRITE(RADEON_BUS_CNTL, tmp);
656+
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
657+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
658+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
659+
/* rs400, rs690/rs740 */
660+
tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS;
661+
RADEON_WRITE(RADEON_BUS_CNTL, tmp);
662+
} else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
663+
((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) {
664+
/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
665+
tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
666+
RADEON_WRITE(RADEON_BUS_CNTL, tmp);
667+
} /* PCIE cards appears to not need this */
657668

658669
dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
659670
RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
@@ -1719,6 +1730,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
17191730
case CHIP_R300:
17201731
case CHIP_R350:
17211732
case CHIP_R420:
1733+
case CHIP_R423:
17221734
case CHIP_RV410:
17231735
case CHIP_RV515:
17241736
case CHIP_R520:

drivers/gpu/drm/radeon/radeon_drv.h

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -122,6 +122,7 @@ enum radeon_family {
122122
CHIP_RV350,
123123
CHIP_RV380,
124124
CHIP_R420,
125+
CHIP_R423,
125126
CHIP_RV410,
126127
CHIP_RS400,
127128
CHIP_RS480,
@@ -439,8 +440,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
439440
# define RADEON_SCISSOR_1_ENABLE (1 << 29)
440441
# define RADEON_SCISSOR_2_ENABLE (1 << 30)
441442

443+
/*
444+
* PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
445+
* don't have an explicit bus mastering disable bit. It's handled
446+
* by the PCI D-states. PMI_BM_DIS disables D-state bus master
447+
* handling, not bus mastering itself.
448+
*/
442449
#define RADEON_BUS_CNTL 0x0030
450+
/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
443451
# define RADEON_BUS_MASTER_DIS (1 << 6)
452+
/* rs400, rs690/rs740 */
453+
# define RS400_BUS_MASTER_DIS (1 << 14)
454+
# define RS400_MSI_REARM (1 << 20)
455+
/* see RS480_MSI_REARM in AIC_CNTL for rs480 */
456+
457+
#define RADEON_BUS_CNTL1 0x0034
458+
# define RADEON_PMI_BM_DIS (1 << 2)
459+
# define RADEON_PMI_INT_DIS (1 << 3)
460+
461+
#define RV370_BUS_CNTL 0x004c
462+
# define RV370_PMI_BM_DIS (1 << 5)
463+
# define RV370_PMI_INT_DIS (1 << 6)
464+
465+
#define RADEON_MSI_REARM_EN 0x0160
466+
/* rv370/rv380, rv410, r423/r430/r480, r5xx */
467+
# define RV370_MSI_REARM_EN (1 << 0)
444468

445469
#define RADEON_CLOCK_CNTL_DATA 0x000c
446470
# define RADEON_PLL_WR_EN (1 << 7)
@@ -913,6 +937,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
913937

914938
#define RADEON_AIC_CNTL 0x01d0
915939
# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
940+
# define RS480_MSI_REARM (1 << 3)
916941
#define RADEON_AIC_STAT 0x01d4
917942
#define RADEON_AIC_PT_BASE 0x01d8
918943
#define RADEON_AIC_LO_ADDR 0x01dc

include/drm/drm_pciids.h

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -84,18 +84,18 @@
8484
{0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
8585
{0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
8686
{0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
87-
{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
88-
{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
89-
{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
90-
{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
91-
{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
92-
{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
93-
{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
94-
{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
95-
{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
96-
{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
97-
{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
98-
{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
87+
{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
88+
{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
89+
{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
90+
{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
91+
{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
92+
{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
93+
{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
94+
{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
95+
{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
96+
{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
97+
{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
98+
{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
9999
{0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
100100
{0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
101101
{0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
@@ -124,16 +124,16 @@
124124
{0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
125125
{0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
126126
{0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
127-
{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
128-
{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
129-
{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
130-
{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
131-
{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
132-
{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
133-
{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
134-
{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
135-
{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
136-
{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
127+
{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
128+
{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
129+
{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
130+
{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
131+
{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
132+
{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
133+
{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
134+
{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
135+
{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
136+
{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
137137
{0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
138138
{0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
139139
{0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \

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