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virtuoso
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intel_th: Add Software Trace Hub driver
Software Trace Hub (STH) is a trace source device in the Intel TH architecture, it generates data that then goes through the switch into one or several output ports. STH collects data from software sources using the stm device class abstraction. Signed-off-by: Alexander Shishkin <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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‎drivers/hwtracing/intel_th/Kconfig

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@@ -34,6 +34,16 @@ config INTEL_TH_GTH
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Say Y here to enable GTH subdevice of Intel(R) Trace Hub.
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config INTEL_TH_STH
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tristate "Intel(R) Trace Hub Software Trace Hub support"
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depends on STM
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help
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Software Trace Hub (STH) enables trace data from software
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trace sources to be sent out via Intel(R) Trace Hub. It
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uses stm class device to interface with its sources.
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Say Y here to enable STH subdevice of Intel(R) Trace Hub.
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config INTEL_TH_DEBUG
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bool "Intel(R) Trace Hub debugging"
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depends on DEBUG_FS

‎drivers/hwtracing/intel_th/Makefile

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@@ -7,3 +7,6 @@ intel_th_pci-y := pci.o
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obj-$(CONFIG_INTEL_TH_GTH) += intel_th_gth.o
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intel_th_gth-y := gth.o
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obj-$(CONFIG_INTEL_TH_STH) += intel_th_sth.o
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intel_th_sth-y := sth.o

‎drivers/hwtracing/intel_th/sth.c

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/*
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* Intel(R) Trace Hub Software Trace Hub support
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*
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* Copyright (C) 2014-2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/stm.h>
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#include "intel_th.h"
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#include "sth.h"
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struct sth_device {
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void __iomem *base;
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void __iomem *channels;
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phys_addr_t channels_phys;
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struct device *dev;
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struct stm_data stm;
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unsigned int sw_nmasters;
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};
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static struct intel_th_channel __iomem *
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sth_channel(struct sth_device *sth, unsigned int master, unsigned int channel)
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{
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struct intel_th_channel __iomem *sw_map = sth->channels;
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return &sw_map[(master - sth->stm.sw_start) * sth->stm.sw_nchannels +
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channel];
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}
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static void sth_iowrite(void __iomem *dest, const unsigned char *payload,
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unsigned int size)
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{
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switch (size) {
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#ifdef CONFIG_64BIT
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case 8:
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writeq_relaxed(*(u64 *)payload, dest);
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break;
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#endif
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case 4:
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writel_relaxed(*(u32 *)payload, dest);
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break;
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case 2:
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writew_relaxed(*(u16 *)payload, dest);
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break;
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case 1:
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writeb_relaxed(*(u8 *)payload, dest);
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break;
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default:
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break;
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}
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}
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static ssize_t sth_stm_packet(struct stm_data *stm_data, unsigned int master,
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unsigned int channel, unsigned int packet,
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unsigned int flags, unsigned int size,
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const unsigned char *payload)
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{
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struct sth_device *sth = container_of(stm_data, struct sth_device, stm);
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struct intel_th_channel __iomem *out =
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sth_channel(sth, master, channel);
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u64 __iomem *outp = &out->Dn;
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unsigned long reg = REG_STH_TRIG;
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#ifndef CONFIG_64BIT
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if (size > 4)
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size = 4;
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#endif
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size = rounddown_pow_of_two(size);
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switch (packet) {
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/* Global packets (GERR, XSYNC, TRIG) are sent with register writes */
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case STP_PACKET_GERR:
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reg += 4;
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case STP_PACKET_XSYNC:
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reg += 8;
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case STP_PACKET_TRIG:
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if (flags & STP_PACKET_TIMESTAMPED)
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reg += 4;
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iowrite8(*payload, sth->base + reg);
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break;
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case STP_PACKET_MERR:
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sth_iowrite(&out->MERR, payload, size);
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break;
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case STP_PACKET_FLAG:
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if (flags & STP_PACKET_TIMESTAMPED)
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outp = (u64 __iomem *)&out->FLAG_TS;
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else
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outp = (u64 __iomem *)&out->FLAG;
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size = 1;
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sth_iowrite(outp, payload, size);
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break;
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case STP_PACKET_USER:
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if (flags & STP_PACKET_TIMESTAMPED)
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outp = &out->USER_TS;
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else
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outp = &out->USER;
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sth_iowrite(outp, payload, size);
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break;
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case STP_PACKET_DATA:
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outp = &out->Dn;
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if (flags & STP_PACKET_TIMESTAMPED)
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outp += 2;
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if (flags & STP_PACKET_MARKED)
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outp++;
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sth_iowrite(outp, payload, size);
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break;
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}
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return size;
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}
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static phys_addr_t
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sth_stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
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unsigned int channel, unsigned int nr_chans)
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{
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struct sth_device *sth = container_of(stm_data, struct sth_device, stm);
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phys_addr_t addr;
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master -= sth->stm.sw_start;
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addr = sth->channels_phys + (master * sth->stm.sw_nchannels + channel) *
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sizeof(struct intel_th_channel);
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if (offset_in_page(addr) ||
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offset_in_page(nr_chans * sizeof(struct intel_th_channel)))
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return 0;
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return addr;
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}
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static int sth_stm_link(struct stm_data *stm_data, unsigned int master,
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unsigned int channel)
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{
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struct sth_device *sth = container_of(stm_data, struct sth_device, stm);
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intel_th_set_output(to_intel_th_device(sth->dev), master);
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return 0;
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}
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static int intel_th_sw_init(struct sth_device *sth)
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{
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u32 reg;
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reg = ioread32(sth->base + REG_STH_STHCAP1);
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sth->stm.sw_nchannels = reg & 0xff;
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reg = ioread32(sth->base + REG_STH_STHCAP0);
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sth->stm.sw_start = reg & 0xffff;
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sth->stm.sw_end = reg >> 16;
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sth->sw_nmasters = sth->stm.sw_end - sth->stm.sw_start;
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dev_dbg(sth->dev, "sw_start: %x sw_end: %x masters: %x nchannels: %x\n",
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sth->stm.sw_start, sth->stm.sw_end, sth->sw_nmasters,
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sth->stm.sw_nchannels);
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return 0;
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}
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static int intel_th_sth_probe(struct intel_th_device *thdev)
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{
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struct device *dev = &thdev->dev;
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struct sth_device *sth;
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struct resource *res;
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void __iomem *base, *channels;
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int err;
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res = intel_th_device_get_resource(thdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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base = devm_ioremap(dev, res->start, resource_size(res));
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if (IS_ERR(base))
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return PTR_ERR(base);
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res = intel_th_device_get_resource(thdev, IORESOURCE_MEM, 1);
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if (!res)
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return -ENODEV;
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channels = devm_ioremap(dev, res->start, resource_size(res));
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if (IS_ERR(channels))
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return PTR_ERR(channels);
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sth = devm_kzalloc(dev, sizeof(*sth), GFP_KERNEL);
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if (!sth)
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return -ENOMEM;
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sth->dev = dev;
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sth->base = base;
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sth->channels = channels;
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sth->channels_phys = res->start;
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sth->stm.name = dev_name(dev);
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sth->stm.packet = sth_stm_packet;
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sth->stm.mmio_addr = sth_stm_mmio_addr;
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sth->stm.sw_mmiosz = sizeof(struct intel_th_channel);
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sth->stm.link = sth_stm_link;
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err = intel_th_sw_init(sth);
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if (err)
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return err;
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err = stm_register_device(dev, &sth->stm, THIS_MODULE);
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if (err) {
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dev_err(dev, "stm_register_device failed\n");
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return err;
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}
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dev_set_drvdata(dev, sth);
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return 0;
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}
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static void intel_th_sth_remove(struct intel_th_device *thdev)
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{
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struct sth_device *sth = dev_get_drvdata(&thdev->dev);
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stm_unregister_device(&sth->stm);
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}
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static struct intel_th_driver intel_th_sth_driver = {
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.probe = intel_th_sth_probe,
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.remove = intel_th_sth_remove,
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.driver = {
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.name = "sth",
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.owner = THIS_MODULE,
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},
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};
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module_driver(intel_th_sth_driver,
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intel_th_driver_register,
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intel_th_driver_unregister);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Intel(R) Trace Hub Software Trace Hub driver");
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MODULE_AUTHOR("Alexander Shishkin <[email protected]>");

‎drivers/hwtracing/intel_th/sth.h

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/*
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* Intel(R) Trace Hub Software Trace Hub (STH) data structures
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*
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* Copyright (C) 2014-2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __INTEL_TH_STH_H__
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#define __INTEL_TH_STH_H__
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enum {
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REG_STH_STHCAP0 = 0x0000, /* capabilities pt1 */
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REG_STH_STHCAP1 = 0x0004, /* capabilities pt2 */
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REG_STH_TRIG = 0x0008, /* TRIG packet payload */
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REG_STH_TRIG_TS = 0x000c, /* TRIG_TS packet payload */
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REG_STH_XSYNC = 0x0010, /* XSYNC packet payload */
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REG_STH_XSYNC_TS = 0x0014, /* XSYNC_TS packet payload */
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REG_STH_GERR = 0x0018, /* GERR packet payload */
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};
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struct intel_th_channel {
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u64 Dn;
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u64 DnM;
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u64 DnTS;
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u64 DnMTS;
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u64 USER;
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u64 USER_TS;
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u32 FLAG;
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u32 FLAG_TS;
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u32 MERR;
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u32 __unused;
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} __packed;
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#endif /* __INTEL_TH_STH_H__ */

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