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Disintegrate asm/system.h for X86
Disintegrate asm/system.h for X86. Signed-off-by: David Howells <[email protected]> Acked-by: H. Peter Anvin <[email protected]> cc: [email protected]
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‎arch/x86/ia32/ia32_aout.c

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#include <linux/init.h>
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#include <linux/jiffies.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/cacheflush.h>

‎arch/x86/include/asm/apic.h

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#include <linux/atomic.h>
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#include <asm/fixmap.h>
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#include <asm/mpspec.h>
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#include <asm/system.h>
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#include <asm/msr.h>
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#define ARCH_APICTIMER_STOPS_ON_C3 1

‎arch/x86/include/asm/auxvec.h

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#endif
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#define AT_SYSINFO_EHDR 33
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/* entries in ARCH_DLINFO: */
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#if defined(CONFIG_IA32_EMULATION) || !defined(CONFIG_X86_64)
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# define AT_VECTOR_SIZE_ARCH 2
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#else /* else it's non-compat x86-64 */
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# define AT_VECTOR_SIZE_ARCH 1
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#endif
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#endif /* _ASM_X86_AUXVEC_H */

‎arch/x86/include/asm/barrier.h

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#ifndef _ASM_X86_BARRIER_H
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#define _ASM_X86_BARRIER_H
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#include <asm/alternative.h>
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#include <asm/nops.h>
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_X86_32
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/*
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* Some non-Intel clones support out of order store. wmb() ceases to be a
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* nop for these.
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*/
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#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
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#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
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#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
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#else
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#endif
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/**
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like this where there are no data dependencies.
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**/
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#define read_barrier_depends() do { } while (0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#ifdef CONFIG_X86_PPRO_FENCE
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# define smp_rmb() rmb()
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#else
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# define smp_rmb() barrier()
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#endif
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#ifdef CONFIG_X86_OOSTORE
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# define smp_wmb() wmb()
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#else
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# define smp_wmb() barrier()
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#endif
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#define smp_read_barrier_depends() read_barrier_depends()
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while (0)
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#define set_mb(var, value) do { var = value; barrier(); } while (0)
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#endif
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/*
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* Stop RDTSC speculation. This is needed when you need to use RDTSC
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* (or get_cycles or vread that possibly accesses the TSC) in a defined
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* code region.
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*
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* (Could use an alternative three way for this if there was one.)
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*/
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static __always_inline void rdtsc_barrier(void)
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{
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alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
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alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
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}
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#endif /* _ASM_X86_BARRIER_H */

‎arch/x86/include/asm/bug.h

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#endif /* !CONFIG_BUG */
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#include <asm-generic/bug.h>
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extern void show_regs_common(void);
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#endif /* _ASM_X86_BUG_H */

‎arch/x86/include/asm/cacheflush.h

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/* Caches aren't brain-dead on the intel. */
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#include <asm-generic/cacheflush.h>
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#include <asm/special_insns.h>
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#ifdef CONFIG_X86_PAT
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/*

‎arch/x86/include/asm/elf.h

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(((x)->e_machine == EM_386) || ((x)->e_machine == EM_486))
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#include <asm/processor.h>
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#include <asm/system.h>
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#ifdef CONFIG_X86_32
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#include <asm/desc.h>

‎arch/x86/include/asm/exec.h

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/* define arch_align_stack() here */

‎arch/x86/include/asm/futex.h

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#include <asm/asm.h>
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#include <asm/errno.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
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asm volatile("1:\t" insn "\n" \

‎arch/x86/include/asm/i387.h

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#include <linux/sched.h>
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#include <linux/hardirq.h>
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#include <asm/system.h>
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struct pt_regs;
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struct user_i387_struct;

‎arch/x86/include/asm/local.h

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#include <linux/percpu.h>
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#include <asm/system.h>
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#include <linux/atomic.h>
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#include <asm/asm.h>
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‎arch/x86/include/asm/mc146818rtc.h

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#define _ASM_X86_MC146818RTC_H
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <linux/mc146818rtc.h>
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‎arch/x86/include/asm/processor.h

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#include <asm/sigcontext.h>
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#include <asm/current.h>
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#include <asm/cpufeature.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/pgtable_types.h>
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#include <asm/percpu.h>
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#include <asm/msr.h>
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#include <asm/desc_defs.h>
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#include <asm/nops.h>
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#include <asm/special_insns.h>
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#include <linux/personality.h>
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#include <linux/cpumask.h>
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#include <linux/math64.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/irqflags.h>
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/*
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* We handle most unaligned accesses in hardware. On the other hand
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* unaligned DMA can be quite expensive on some Nehalem processors.
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*
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* Based on this we disable the IP header alignment in network drivers.
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*/
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#define NET_IP_ALIGN 0
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#define HBP_NUM 4
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/*
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#define cpu_has_amd_erratum(x) (false)
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#endif /* CONFIG_CPU_SUP_AMD */
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#ifdef CONFIG_X86_32
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/*
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* disable hlt during certain critical i/o operations
1037+
*/
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#define HAVE_DISABLE_HLT
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#endif
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void disable_hlt(void);
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void enable_hlt(void);
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void cpu_idle_wait(void);
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extern unsigned long arch_align_stack(unsigned long sp);
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extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
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void default_idle(void);
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bool set_pm_idle_to_default(void);
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void stop_this_cpu(void *dummy);
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#endif /* _ASM_X86_PROCESSOR_H */

‎arch/x86/include/asm/segment.h

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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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extern const char early_idt_handlers[NUM_EXCEPTION_VECTORS][10];
215-
#endif
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#endif
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/*
217+
* Load a segment. Fall back on loading the zero
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* segment if something goes wrong..
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*/
220+
#define loadsegment(seg, value) \
221+
do { \
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unsigned short __val = (value); \
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\
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asm volatile(" \n" \
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"1: movl %k0,%%" #seg " \n" \
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\
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".section .fixup,\"ax\" \n" \
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"2: xorl %k0,%k0 \n" \
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" jmp 1b \n" \
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".previous \n" \
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\
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_ASM_EXTABLE(1b, 2b) \
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\
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: "+r" (__val) : : "memory"); \
235+
} while (0)
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/*
238+
* Save a segment register away
239+
*/
240+
#define savesegment(seg, value) \
241+
asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
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/*
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* x86_32 user gs accessors.
245+
*/
246+
#ifdef CONFIG_X86_32
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#ifdef CONFIG_X86_32_LAZY_GS
248+
#define get_user_gs(regs) (u16)({unsigned long v; savesegment(gs, v); v;})
249+
#define set_user_gs(regs, v) loadsegment(gs, (unsigned long)(v))
250+
#define task_user_gs(tsk) ((tsk)->thread.gs)
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#define lazy_save_gs(v) savesegment(gs, (v))
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#define lazy_load_gs(v) loadsegment(gs, (v))
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#else /* X86_32_LAZY_GS */
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#define get_user_gs(regs) (u16)((regs)->gs)
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#define set_user_gs(regs, v) do { (regs)->gs = (v); } while (0)
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#define task_user_gs(tsk) (task_pt_regs(tsk)->gs)
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#define lazy_save_gs(v) do { } while (0)
258+
#define lazy_load_gs(v) do { } while (0)
259+
#endif /* X86_32_LAZY_GS */
260+
#endif /* X86_32 */
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static inline unsigned long get_limit(unsigned long segment)
263+
{
264+
unsigned long __limit;
265+
asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
266+
return __limit + 1;
267+
}
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269+
#endif /* !__ASSEMBLY__ */
270+
#endif /* __KERNEL__ */
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#endif /* _ASM_X86_SEGMENT_H */

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