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drm/radeon: add support for RS740 IGP chipsets.
This adds support for the HS2100 IGP chipset. Signed-off-by: Dave Airlie <[email protected]>
1 parent b612eda commit f0738e9

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3 files changed

+23
-9
lines changed

3 files changed

+23
-9
lines changed

‎drivers/gpu/drm/radeon/radeon_cp.c

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,8 @@ static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
7171

7272
static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
7373
{
74-
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
74+
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
75+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
7576
return RS690_READ_MCIND(dev_priv, addr);
7677
else
7778
return RS480_READ_MCIND(dev_priv, addr);
@@ -82,7 +83,8 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
8283

8384
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
8485
return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
85-
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
86+
else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
87+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
8688
return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
8789
else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
8890
return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
@@ -94,7 +96,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
9496
{
9597
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
9698
R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
97-
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
99+
else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
100+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
98101
RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
99102
else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
100103
R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
@@ -106,7 +109,8 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
106109
{
107110
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
108111
R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
109-
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
112+
else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
113+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
110114
RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
111115
else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
112116
R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
@@ -122,7 +126,8 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
122126
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
123127
R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
124128
R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
125-
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
129+
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
130+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
126131
RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
127132
RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
128133
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
@@ -364,8 +369,9 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
364369
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
365370
R420_cp_microcode[i][0]);
366371
}
367-
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
368-
DRM_INFO("Loading RS690 Microcode\n");
372+
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
373+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
374+
DRM_INFO("Loading RS690/RS740 Microcode\n");
369375
for (i = 0; i < 256; i++) {
370376
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
371377
RS690_cp_microcode[i][1]);
@@ -720,7 +726,8 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
720726
dev_priv->gart_size);
721727

722728
temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
723-
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
729+
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
730+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
724731
IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
725732
RS690_BLOCK_GFX_D3_EN));
726733
else
@@ -813,6 +820,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
813820
u32 tmp;
814821

815822
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
823+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
816824
(dev_priv->flags & RADEON_IS_IGPGART)) {
817825
radeon_set_igpgart(dev_priv, on);
818826
return;

‎drivers/gpu/drm/radeon/radeon_drv.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,7 @@ enum radeon_family {
125125
CHIP_RV410,
126126
CHIP_RS480,
127127
CHIP_RS690,
128+
CHIP_RS740,
128129
CHIP_RV515,
129130
CHIP_R520,
130131
CHIP_RV530,
@@ -1207,7 +1208,8 @@ do { \
12071208

12081209
#define IGP_WRITE_MCIND(addr, val) \
12091210
do { \
1210-
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1211+
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1212+
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
12111213
RS690_WRITE_MCIND(addr, val); \
12121214
else \
12131215
RS480_WRITE_MCIND(addr, val); \

‎include/drm/drm_pciids.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -237,6 +237,10 @@
237237
{0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
238238
{0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
239239
{0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
240+
{0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
241+
{0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
242+
{0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
243+
{0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
240244
{0, 0, 0}
241245

242246
#define r128_PCI_IDS \

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