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Merge branch 'omap-for-v4.15/fixes-dt' into omap-for-v4.15/ti-sysc
2 parents 10e998f + 160ec89 commit f09de60

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Documentation/devicetree/bindings/arm/omap/ctrl.txt

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@@ -21,6 +21,8 @@ Required properties:
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"ti,omap3-scm"
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"ti,omap4-scm-core"
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"ti,omap4-scm-padconf-core"
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"ti,omap4-scm-wkup"
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"ti,omap4-scm-padconf-wkup"
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"ti,omap5-scm-core"
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"ti,omap5-scm-padconf-core"
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"ti,dra7-scm-core"
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Texas Instruments sysc interconnect target module wrapper binding
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Texas Instruments SoCs can have a generic interconnect target module
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hardware for devices connected to various interconnects such as L3
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interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
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is mostly used for interaction between module and PRCM. It participates
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in the OCP Disconnect Protocol but other than that is mostly independent
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of the interconnect.
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Each interconnect target module can have one or more devices connected to
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it. There is a set of control registers for managing interconnect target
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module clocks, idle modes and interconnect level resets for the module.
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These control registers are sprinkled into the unused register address
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space of the first child device IP block managed by the interconnect
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target module and typically are named REVISION, SYSCONFIG and SYSSTATUS.
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Required standard properties:
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- compatible shall be one of the following generic types:
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"ti,sysc-omap2"
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"ti,sysc-omap4"
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"ti,sysc-omap4-simple"
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or one of the following derivative types for hardware
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needing special workarounds:
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"ti,sysc-omap3430-sr"
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"ti,sysc-omap3630-sr"
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"ti,sysc-omap4-sr"
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"ti,sysc-omap3-sham"
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"ti,sysc-omap-aes"
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"ti,sysc-mcasp"
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"ti,sysc-usb-host-fs"
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- reg shall have register areas implemented for the interconnect
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target module in question such as revision, sysc and syss
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- reg-names shall contain the register names implemented for the
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interconnect target module in question such as
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"rev, "sysc", and "syss"
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- ranges shall contain the interconnect target module IO range
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available for one or more child device IP blocks managed
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by the interconnect target module, the ranges may include
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multiple ranges such as device L4 range for control and
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parent L3 range for DMA access
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Optional properties:
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- clocks clock specifier for each name in the clock-names as
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specified in the binding documentation for ti-clkctrl,
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typically available for all interconnect targets on TI SoCs
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based on omap4 except if it's read-only register in hwauto
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mode as for example omap4 L4_CFG_CLKCTRL
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- clock-names should contain at least "fck", and optionally also "ick"
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depending on the SoC and the interconnect target module
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- ti,hwmods optional TI interconnect module name to use legacy
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hwmod platform data
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Example: Single instance of MUSB controller on omap4 using interconnect ranges
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using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
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target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
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compatible = "ti,sysc-omap2";
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ti,hwmods = "usb_otg_hs";
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reg = <0x2b400 0x4>,
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<0x2b404 0x4>,
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<0x2b408 0x4>;
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reg-names = "rev", "sysc", "syss";
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clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2b000 0x1000>;
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usb_otg_hs: otg@0 {
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compatible = "ti,omap4-musb";
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reg = <0x0 0x7ff>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy>;
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...
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};
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};
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Note that other SoCs, such as am335x can have multipe child devices. On am335x
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there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
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instance as children of a single interconnet target module.

Documentation/devicetree/bindings/hsi/omap-ssi.txt

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OMAP SSI controller bindings
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3-
OMAP Synchronous Serial Interface (SSI) controller implements a legacy
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variant of MIPI's High Speed Synchronous Serial Interface (HSI).
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OMAP3's Synchronous Serial Interface (SSI) controller implements a
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legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI),
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while the controller found inside OMAP4 is supposed to be fully compliant
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with the HSI standard.
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Required properties:
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- compatible: Should include "ti,omap3-ssi".
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- compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
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- reg-names: Contains the values "sys" and "gdd" (in this order).
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- reg: Contains a matching register specifier for each entry
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in reg-names.
@@ -27,6 +29,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device.
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Required Port sub-node properties:
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- compatible: Should be set to the following value
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ti,omap3-ssi-port (applicable to OMAP34xx devices)
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ti,omap4-hsi-port (applicable to OMAP44xx devices)
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- reg-names: Contains the values "tx" and "rx" (in this order).
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- reg: Contains a matching register specifier for each entry
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in reg-names.
@@ -38,6 +41,10 @@ Required Port sub-node properties:
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property. If it's missing the port will not be
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enabled.
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Optional properties:
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- ti,hwmods: Shall contain TI interconnect module name if needed
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by the SoC
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Example for Nokia N900:
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ssi-controller@48058000 {

Documentation/devicetree/bindings/memory-controllers/ti/emif.txt

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@@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it.
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Required properties:
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- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
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is the IP revision of the specific EMIF instance.
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For am437x should be ti,emif-am4372.
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is the IP revision of the specific EMIF instance. For newer controllers,
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compatible should be one of the following:
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"ti,emif-am3352"
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"ti,emif-am4372"
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- phy-type : <u32> indicating the DDR phy type. Following are the
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allowed values
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Texas Instruments SmartReflex binding
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SmartReflex is used to set and adjust the SoC operating points.
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Required properties:
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compatible: Shall be one of the following:
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"ti,omap3-smartreflex-core"
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"ti,omap3-smartreflex-iva"
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"ti,omap4-smartreflex-core"
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"ti,omap4-smartreflex-mpu"
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"ti,omap4-smartreflex-iva"
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reg: Shall contain the device instance IO range
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interrupts: Shall contain the device instance interrupt
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Optional properties:
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ti,hwmods: Shall contain the TI interconnect module name if needed
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by the SoC
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Example:
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smartreflex_iva: smartreflex@4a0db000 {
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compatible = "ti,omap4-smartreflex-iva";
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reg = <0x4a0db000 0x80>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "smartreflex_iva";
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};
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smartreflex_core: smartreflex@4a0dd000 {
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compatible = "ti,omap4-smartreflex-core";
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reg = <0x4a0dd000 0x80>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "smartreflex_core";
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};
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smartreflex_mpu: smartreflex@4a0d9000 {
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compatible = "ti,omap4-smartreflex-mpu";
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reg = <0x4a0d9000 0x80>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "smartreflex_mpu";
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};

arch/arm/boot/dts/am33xx.dtsi

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};
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};
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pmu {
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pmu@4b000000 {
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compatible = "arm,cortex-a8-pmu";
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interrupts = <3>;
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reg = <0x4b000000 0x1000000>;
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ti,hwmods = "debugss";
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};
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/*
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};
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};
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emif: emif@4c000000 {
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compatible = "ti,emif-am3352";
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reg = <0x4c000000 0x1000000>;
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ti,hwmods = "emif";
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";

arch/arm/boot/dts/dra7.dtsi

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#dma-cells = <1>;
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dma-channels = <32>;
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dma-requests = <127>;
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ti,hwmods = "dma_system";
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};
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edma: edma@43300000 {
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max-frequency = <192000000>;
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};
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hdqw1w: 1w@480b2000 {
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compatible = "ti,omap3-1w";
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reg = <0x480b2000 0x1000>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "hdq1w";
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};
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mmc2: mmc@480b4000 {
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compatible = "ti,omap4-hsmmc";
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reg = <0x480b4000 0x400>;
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};
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};
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target-module@4a0dd000 {
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compatible = "ti,sysc-omap4-sr";
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ti,hwmods = "smartreflex_core";
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reg = <0x4a0dd000 0x4>,
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<0x4a0dd008 0x4>;
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reg-names = "rev", "sysc";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x4a0dd000 0x001000>;
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/* SmartReflex child device marked reserved in TRM */
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};
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target-module@4a0d9000 {
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compatible = "ti,sysc-omap4-sr";
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ti,hwmods = "smartreflex_mpu";
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reg = <0x4a0d9000 0x4>,
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<0x4a0d9008 0x4>;
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reg-names = "rev", "sysc";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x4a0d9000 0x001000>;
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/* SmartReflex child device marked reserved in TRM */
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};
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omap_dwc3_1: omap_dwc3_1@48880000 {
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compatible = "ti,dwc3";
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ti,hwmods = "usb_otg_ss1";

arch/arm/boot/dts/omap3.dtsi

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#dma-cells = <1>;
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dma-channels = <32>;
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dma-requests = <96>;
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ti,hwmods = "dma";
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};
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gpio1: gpio@48310000 {

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