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petegriffinjfvogel
petegriffin
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jfvogel
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pinctrl: samsung: add support for eint_fltcon_offset
commit 701d0e910955627734917c3587258aa7e73068bb upstream. On gs101 SoC the fltcon0 (filter configuration 0) offset isn't at a fixed offset like previous SoCs as the fltcon1 register only exists when there are more than 4 pins in the bank. Add a eint_fltcon_offset and new GS101_PIN_BANK_EINT* macros that take an additional fltcon_offs variable. This can then be used in suspend/resume callbacks to save and restore the fltcon0 and fltcon1 registers. Fixes: 4a8be01 ("pinctrl: samsung: Add gs101 SoC pinctrl configuration") Cc: [email protected] Reviewed-by: André Draszik <[email protected]> Signed-off-by: Peter Griffin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]> (cherry picked from commit de08212061ea6991c1ef6ae294b675c74875c9c7) Signed-off-by: Jack Vogel <[email protected]>
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‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

Lines changed: 49 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -939,83 +939,83 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
939939

940940
/* pin banks of gs101 pin-controller (ALIVE) */
941941
static const struct samsung_pin_bank_data gs101_pin_alive[] = {
942-
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00),
943-
EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04),
944-
EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08),
945-
EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c),
946-
EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10),
947-
EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14),
948-
EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18),
949-
EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c),
942+
GS101_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00),
943+
GS101_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08),
944+
GS101_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10),
945+
GS101_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18),
946+
GS101_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c),
947+
GS101_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20),
948+
GS101_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28),
949+
GS101_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30),
950950
};
951951

952952
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
953953
static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
954-
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00),
955-
EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04),
956-
EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08),
957-
EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c),
954+
GS101_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00),
955+
GS101_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08),
956+
GS101_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c),
957+
GS101_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14),
958958
};
959959

960960
/* pin banks of gs101 pin-controller (GSACORE) */
961961
static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
962-
EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00),
963-
EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04),
964-
EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08),
962+
GS101_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00),
963+
GS101_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04),
964+
GS101_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c),
965965
};
966966

967967
/* pin banks of gs101 pin-controller (GSACTRL) */
968968
static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
969-
EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00),
969+
GS101_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00),
970970
};
971971

972972
/* pin banks of gs101 pin-controller (PERIC0) */
973973
static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
974-
EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00),
975-
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04),
976-
EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08),
977-
EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c),
978-
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10),
979-
EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14),
980-
EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18),
981-
EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c),
982-
EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20),
983-
EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24),
984-
EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28),
985-
EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c),
986-
EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30),
987-
EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34),
988-
EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38),
989-
EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c),
990-
EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40),
991-
EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44),
992-
EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48),
993-
EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c),
974+
GS101_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00),
975+
GS101_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08),
976+
GS101_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c),
977+
GS101_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10),
978+
GS101_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14),
979+
GS101_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18),
980+
GS101_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c),
981+
GS101_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20),
982+
GS101_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24),
983+
GS101_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28),
984+
GS101_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c),
985+
GS101_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30),
986+
GS101_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34),
987+
GS101_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38),
988+
GS101_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c),
989+
GS101_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40),
990+
GS101_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44),
991+
GS101_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48),
992+
GS101_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c),
993+
GS101_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50),
994994
};
995995

996996
/* pin banks of gs101 pin-controller (PERIC1) */
997997
static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
998-
EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00),
999-
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04),
1000-
EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08),
1001-
EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c),
1002-
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10),
1003-
EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14),
1004-
EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18),
1005-
EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c),
998+
GS101_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00),
999+
GS101_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08),
1000+
GS101_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c),
1001+
GS101_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10),
1002+
GS101_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18),
1003+
GS101_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c),
1004+
GS101_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20),
1005+
GS101_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28),
10061006
};
10071007

10081008
/* pin banks of gs101 pin-controller (HSI1) */
10091009
static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
1010-
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00),
1011-
EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04),
1010+
GS101_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00),
1011+
GS101_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08),
10121012
};
10131013

10141014
/* pin banks of gs101 pin-controller (HSI2) */
10151015
static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
1016-
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00),
1017-
EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04),
1018-
EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08),
1016+
GS101_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00),
1017+
GS101_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08),
1018+
GS101_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c),
10191019
};
10201020

10211021
static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {

‎drivers/pinctrl/samsung/pinctrl-exynos.h

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -165,6 +165,28 @@
165165
.name = id \
166166
}
167167

168+
#define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \
169+
{ \
170+
.type = &exynos850_bank_type_off, \
171+
.pctl_offset = reg, \
172+
.nr_pins = pins, \
173+
.eint_type = EINT_TYPE_GPIO, \
174+
.eint_offset = offs, \
175+
.eint_fltcon_offset = fltcon_offs, \
176+
.name = id \
177+
}
178+
179+
#define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \
180+
{ \
181+
.type = &exynos850_bank_type_alive, \
182+
.pctl_offset = reg, \
183+
.nr_pins = pins, \
184+
.eint_type = EINT_TYPE_WKUP, \
185+
.eint_offset = offs, \
186+
.eint_fltcon_offset = fltcon_offs, \
187+
.name = id \
188+
}
189+
168190
/**
169191
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
170192
* generated by the external wakeup interrupt controller.

‎drivers/pinctrl/samsung/pinctrl-samsung.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1230,6 +1230,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
12301230
bank->eint_con_offset = bdata->eint_con_offset;
12311231
bank->eint_mask_offset = bdata->eint_mask_offset;
12321232
bank->eint_pend_offset = bdata->eint_pend_offset;
1233+
bank->eint_fltcon_offset = bdata->eint_fltcon_offset;
12331234
bank->name = bdata->name;
12341235

12351236
raw_spin_lock_init(&bank->slock);

‎drivers/pinctrl/samsung/pinctrl-samsung.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,7 @@ struct samsung_pin_bank_type {
144144
* @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
145145
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
146146
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
147+
* @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
147148
* @name: name to be prefixed for each pin in this pin bank.
148149
*/
149150
struct samsung_pin_bank_data {
@@ -158,6 +159,7 @@ struct samsung_pin_bank_data {
158159
u32 eint_con_offset;
159160
u32 eint_mask_offset;
160161
u32 eint_pend_offset;
162+
u32 eint_fltcon_offset;
161163
const char *name;
162164
};
163165

@@ -175,6 +177,7 @@ struct samsung_pin_bank_data {
175177
* @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
176178
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
177179
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
180+
* @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
178181
* @name: name to be prefixed for each pin in this pin bank.
179182
* @id: id of the bank, propagated to the pin range.
180183
* @pin_base: starting pin number of the bank.
@@ -201,6 +204,7 @@ struct samsung_pin_bank {
201204
u32 eint_con_offset;
202205
u32 eint_mask_offset;
203206
u32 eint_pend_offset;
207+
u32 eint_fltcon_offset;
204208
const char *name;
205209
u32 id;
206210

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