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LoongArch: Add CPU definition headers
Add common headers (CPU definition and address space layout) for basic LoongArch support. Reviewed-by: WANG Xuerui <[email protected]> Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Huacai Chen <[email protected]>
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‎arch/loongarch/include/asm/addrspace.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 1996, 99 Ralf Baechle
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* Copyright (C) 2000, 2002 Maciej W. Rozycki
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* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
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*/
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#ifndef _ASM_ADDRSPACE_H
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#define _ASM_ADDRSPACE_H
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#include <linux/const.h>
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#include <asm/loongarch.h>
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/*
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* This gives the physical RAM offset.
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*/
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#ifndef __ASSEMBLY__
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#ifndef PHYS_OFFSET
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#define PHYS_OFFSET _AC(0, UL)
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#endif
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extern unsigned long vm_map_base;
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#endif /* __ASSEMBLY__ */
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#ifndef IO_BASE
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#define IO_BASE CSR_DMW0_BASE
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#endif
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#ifndef CACHE_BASE
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#define CACHE_BASE CSR_DMW1_BASE
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#endif
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#ifndef UNCACHE_BASE
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#define UNCACHE_BASE CSR_DMW0_BASE
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#endif
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#define DMW_PABITS 48
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#define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1)
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/*
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* Memory above this physical address will be considered highmem.
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*/
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#ifndef HIGHMEM_START
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#define HIGHMEM_START (_AC(1, UL) << _AC(DMW_PABITS, UL))
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#endif
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#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
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#define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK))
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#define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK))
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/*
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* This handles the memory map.
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*/
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#ifndef PAGE_OFFSET
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#define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET)
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#endif
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#ifndef FIXADDR_TOP
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#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
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#endif
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#ifdef __ASSEMBLY__
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#define _ATYPE_
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#define _ATYPE32_
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#define _ATYPE64_
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#define _CONST64_(x) x
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#else
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#define _ATYPE_ __PTRDIFF_TYPE__
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#define _ATYPE32_ int
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#define _ATYPE64_ __s64
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#ifdef CONFIG_64BIT
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#define _CONST64_(x) x ## L
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#else
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#define _CONST64_(x) x ## LL
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#endif
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#endif
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/*
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* 32/64-bit LoongArch address spaces
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*/
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#ifdef __ASSEMBLY__
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#define _ACAST32_
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#define _ACAST64_
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#else
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#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
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#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
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#endif
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#ifdef CONFIG_32BIT
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#define UVRANGE 0x00000000
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#define KPRANGE0 0x80000000
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#define KPRANGE1 0xa0000000
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#define KVRANGE 0xc0000000
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#else
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#define XUVRANGE _CONST64_(0x0000000000000000)
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#define XSPRANGE _CONST64_(0x4000000000000000)
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#define XKPRANGE _CONST64_(0x8000000000000000)
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#define XKVRANGE _CONST64_(0xc000000000000000)
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#endif
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/*
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* Returns the physical address of a KPRANGEx / XKPRANGE address
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*/
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#define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
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#endif /* _ASM_ADDRSPACE_H */

‎arch/loongarch/include/asm/cpu-features.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#ifndef __ASM_CPU_FEATURES_H
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#define __ASM_CPU_FEATURES_H
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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#define cpu_opt(opt) (cpu_data[0].options & (opt))
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#define cpu_has(feat) (cpu_data[0].options & BIT_ULL(feat))
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#define cpu_has_loongarch (cpu_has_loongarch32 | cpu_has_loongarch64)
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#define cpu_has_loongarch32 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_32BIT)
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#define cpu_has_loongarch64 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT)
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#define cpu_icache_line_size() cpu_data[0].icache.linesz
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#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
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#define cpu_vcache_line_size() cpu_data[0].vcache.linesz
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#define cpu_scache_line_size() cpu_data[0].scache.linesz
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#ifdef CONFIG_32BIT
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# define cpu_has_64bits (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT)
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# define cpu_vabits 31
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# define cpu_pabits 31
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#endif
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#ifdef CONFIG_64BIT
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# define cpu_has_64bits 1
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# define cpu_vabits cpu_data[0].vabits
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# define cpu_pabits cpu_data[0].pabits
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# define __NEED_ADDRBITS_PROBE
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#endif
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/*
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* SMP assumption: Options of CPU 0 are a superset of all processors.
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* This is true for all known LoongArch systems.
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*/
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#define cpu_has_cpucfg cpu_opt(LOONGARCH_CPU_CPUCFG)
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#define cpu_has_lam cpu_opt(LOONGARCH_CPU_LAM)
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#define cpu_has_ual cpu_opt(LOONGARCH_CPU_UAL)
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#define cpu_has_fpu cpu_opt(LOONGARCH_CPU_FPU)
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#define cpu_has_lsx cpu_opt(LOONGARCH_CPU_LSX)
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#define cpu_has_lasx cpu_opt(LOONGARCH_CPU_LASX)
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#define cpu_has_complex cpu_opt(LOONGARCH_CPU_COMPLEX)
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#define cpu_has_crypto cpu_opt(LOONGARCH_CPU_CRYPTO)
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#define cpu_has_lvz cpu_opt(LOONGARCH_CPU_LVZ)
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#define cpu_has_lbt_x86 cpu_opt(LOONGARCH_CPU_LBT_X86)
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#define cpu_has_lbt_arm cpu_opt(LOONGARCH_CPU_LBT_ARM)
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#define cpu_has_lbt_mips cpu_opt(LOONGARCH_CPU_LBT_MIPS)
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#define cpu_has_lbt (cpu_has_lbt_x86|cpu_has_lbt_arm|cpu_has_lbt_mips)
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#define cpu_has_csr cpu_opt(LOONGARCH_CPU_CSR)
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#define cpu_has_tlb cpu_opt(LOONGARCH_CPU_TLB)
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#define cpu_has_watch cpu_opt(LOONGARCH_CPU_WATCH)
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#define cpu_has_vint cpu_opt(LOONGARCH_CPU_VINT)
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#define cpu_has_csripi cpu_opt(LOONGARCH_CPU_CSRIPI)
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#define cpu_has_extioi cpu_opt(LOONGARCH_CPU_EXTIOI)
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#define cpu_has_prefetch cpu_opt(LOONGARCH_CPU_PREFETCH)
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#define cpu_has_pmp cpu_opt(LOONGARCH_CPU_PMP)
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#define cpu_has_perf cpu_opt(LOONGARCH_CPU_PMP)
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#define cpu_has_scalefreq cpu_opt(LOONGARCH_CPU_SCALEFREQ)
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#define cpu_has_flatmode cpu_opt(LOONGARCH_CPU_FLATMODE)
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#define cpu_has_eiodecode cpu_opt(LOONGARCH_CPU_EIODECODE)
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#define cpu_has_guestid cpu_opt(LOONGARCH_CPU_GUESTID)
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#define cpu_has_hypervisor cpu_opt(LOONGARCH_CPU_HYPERVISOR)
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#endif /* __ASM_CPU_FEATURES_H */

‎arch/loongarch/include/asm/cpu-info.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_CPU_INFO_H
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#define __ASM_CPU_INFO_H
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#include <linux/cache.h>
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#include <linux/types.h>
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#include <asm/loongarch.h>
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/*
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* Descriptor for a cache
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*/
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struct cache_desc {
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unsigned int waysize; /* Bytes per way */
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unsigned short sets; /* Number of lines per set */
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unsigned char ways; /* Number of ways */
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unsigned char linesz; /* Size of line in bytes */
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unsigned char waybit; /* Bits to select in a cache set */
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unsigned char flags; /* Flags describing cache properties */
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};
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struct cpuinfo_loongarch {
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u64 asid_cache;
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unsigned long asid_mask;
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/*
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* Capability and feature descriptor structure for LoongArch CPU
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*/
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unsigned long long options;
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unsigned int processor_id;
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unsigned int fpu_vers;
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unsigned int fpu_csr0;
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unsigned int fpu_mask;
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unsigned int cputype;
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int isa_level;
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int tlbsize;
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int tlbsizemtlb;
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int tlbsizestlbsets;
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int tlbsizestlbways;
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struct cache_desc icache; /* Primary I-cache */
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struct cache_desc dcache; /* Primary D or combined I/D cache */
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struct cache_desc vcache; /* Victim cache, between pcache and scache */
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struct cache_desc scache; /* Secondary cache */
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struct cache_desc tcache; /* Tertiary/split secondary cache */
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int core; /* physical core number in package */
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int package;/* physical package number */
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int vabits; /* Virtual Address size in bits */
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int pabits; /* Physical Address size in bits */
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unsigned int ksave_mask; /* Usable KSave mask. */
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unsigned int watch_dreg_count; /* Number data breakpoints */
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unsigned int watch_ireg_count; /* Number instruction breakpoints */
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unsigned int watch_reg_use_cnt; /* min(NUM_WATCH_REGS, watch_dreg_count + watch_ireg_count), Usable by ptrace */
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} __aligned(SMP_CACHE_BYTES);
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extern struct cpuinfo_loongarch cpu_data[];
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#define boot_cpu_data cpu_data[0]
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#define current_cpu_data cpu_data[smp_processor_id()]
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#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
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extern void cpu_probe(void);
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extern const char *__cpu_family[];
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extern const char *__cpu_full_name[];
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#define cpu_family_string() __cpu_family[raw_smp_processor_id()]
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#define cpu_full_name_string() __cpu_full_name[raw_smp_processor_id()]
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struct seq_file;
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struct notifier_block;
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extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
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extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
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#define proc_cpuinfo_notifier(fn, pri) \
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({ \
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static struct notifier_block fn##_nb = { \
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.notifier_call = fn, \
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.priority = pri \
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}; \
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\
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register_proc_cpuinfo_notifier(&fn##_nb); \
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})
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struct proc_cpuinfo_notifier_args {
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struct seq_file *m;
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unsigned long n;
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};
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static inline bool cpus_are_siblings(int cpua, int cpub)
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{
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struct cpuinfo_loongarch *infoa = &cpu_data[cpua];
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struct cpuinfo_loongarch *infob = &cpu_data[cpub];
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if (infoa->package != infob->package)
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return false;
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if (infoa->core != infob->core)
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return false;
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return true;
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}
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static inline unsigned long cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo)
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{
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return cpuinfo->asid_mask;
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}
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static inline void set_cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo,
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unsigned long asid_mask)
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{
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cpuinfo->asid_mask = asid_mask;
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}
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#endif /* __ASM_CPU_INFO_H */

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