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251 | 251 | dma@c300 {
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252 | 252 | #address-cells = <1>;
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253 | 253 | #size-cells = <1>;
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254 |
| - compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma"; |
| 254 | + compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma"; |
255 | 255 | cell-index = <1>;
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256 | 256 | reg = <0xc300 0x4>; /* DMA general status register */
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257 | 257 | ranges = <0x0 0xc100 0x200>;
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258 | 258 |
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259 | 259 | dma-channel@0 {
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260 | 260 | compatible = "fsl,mpc8610-dma-channel",
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261 |
| - "fsl,mpc8540-dma-channel"; |
| 261 | + "fsl,eloplus-dma-channel"; |
262 | 262 | cell-index = <0>;
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263 | 263 | reg = <0x0 0x80>;
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264 | 264 | interrupt-parent = <&mpic>;
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265 | 265 | interrupts = <60 2>;
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266 | 266 | };
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267 | 267 | dma-channel@1 {
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268 | 268 | compatible = "fsl,mpc8610-dma-channel",
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269 |
| - "fsl,mpc8540-dma-channel"; |
| 269 | + "fsl,eloplus-dma-channel"; |
270 | 270 | cell-index = <1>;
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271 | 271 | reg = <0x80 0x80>;
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272 | 272 | interrupt-parent = <&mpic>;
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273 | 273 | interrupts = <61 2>;
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274 | 274 | };
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275 | 275 | dma-channel@2 {
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276 | 276 | compatible = "fsl,mpc8610-dma-channel",
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277 |
| - "fsl,mpc8540-dma-channel"; |
| 277 | + "fsl,eloplus-dma-channel"; |
278 | 278 | cell-index = <2>;
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279 | 279 | reg = <0x100 0x80>;
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280 | 280 | interrupt-parent = <&mpic>;
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281 | 281 | interrupts = <62 2>;
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282 | 282 | };
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283 | 283 | dma-channel@3 {
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284 | 284 | compatible = "fsl,mpc8610-dma-channel",
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285 |
| - "fsl,mpc8540-dma-channel"; |
| 285 | + "fsl,eloplus-dma-channel"; |
286 | 286 | cell-index = <3>;
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287 | 287 | reg = <0x180 0x80>;
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288 | 288 | interrupt-parent = <&mpic>;
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