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phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver
This patch adds support for R-Car generation 3 USB2 PHY driver. This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared with the HSUSB (USB2.0 peripheral) device. And each channel has independent registers about the PHYs. So, the purpose of this driver is: 1) initializes some registers of SoC specific to use the {ehci,ohci}-platform driver. 2) detects id pin to select host or peripheral on the channel 0. For now, this driver only supports 1) above. Signed-off-by: Yoshihiro Shimoda <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
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‎Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt

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* Renesas R-Car generation 3 USB 2.0 PHY
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This file provides information on what the device node for the R-Car generation
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3 USB 2.0 PHY contains.
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Required properties:
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- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
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SoC.
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- reg: offset and length of the partial USB 2.0 Host register block.
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- reg-names: must be "usb2_host".
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- clocks: clock phandle and specifier pair(s).
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- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
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Optional properties:
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To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are
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combined, the device tree node should set HSUSB properties to reg and reg-names
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properties. This is because HSUSB has registers to select USB 2.0 host or
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peripheral at that channel:
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- reg: offset and length of the partial HSUSB register block.
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- reg-names: must be "hsusb".
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Example (R-Car H3):
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usb-phy@ee080200 {
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compatible = "renesas,usb2-phy-r8a7795";
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reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>;
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reg-names = "usb2_host", "hsusb";
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clocks = <&mstp7_clks R8A7795_CLK_EHCI0>,
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<&mstp7_clks R8A7795_CLK_HSUSB>;
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};
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usb-phy@ee0a0200 {
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compatible = "renesas,usb2-phy-r8a7795";
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reg = <0 0xee0a0200 0 0x700>;
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reg-names = "usb2_host";
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clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
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};

‎drivers/phy/Kconfig

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@@ -118,6 +118,13 @@ config PHY_RCAR_GEN2
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help
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Support for USB PHY found on Renesas R-Car generation 2 SoCs.
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config PHY_RCAR_GEN3_USB2
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tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
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depends on OF && ARCH_SHMOBILE
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select GENERIC_PHY
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help
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Support for USB 2.0 PHY found on Renesas R-Car generation 3 SoCs.
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config OMAP_CONTROL_PHY
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tristate "OMAP CONTROL PHY Driver"
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depends on ARCH_OMAP2PLUS || COMPILE_TEST

‎drivers/phy/Makefile

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@@ -17,6 +17,7 @@ obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
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obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o
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obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o
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obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
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obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o
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obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
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obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
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obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o

‎drivers/phy/phy-rcar-gen3-usb2.c

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/*
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* Renesas R-Car Gen3 for USB2.0 PHY driver
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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*
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* This is based on the phy-rcar-gen2 driver:
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* Copyright (C) 2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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/******* USB2.0 Host registers (original offset is +0x200) *******/
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#define USB2_INT_ENABLE 0x000
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#define USB2_USBCTR 0x00c
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#define USB2_SPD_RSM_TIMSET 0x10c
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#define USB2_OC_TIMSET 0x110
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/* INT_ENABLE */
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#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
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#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
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#define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_USBH_INTB_EN | \
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USB2_INT_ENABLE_USBH_INTA_EN)
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/* USBCTR */
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#define USB2_USBCTR_DIRPD BIT(2)
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#define USB2_USBCTR_PLL_RST BIT(1)
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/* SPD_RSM_TIMSET */
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#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
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/* OC_TIMSET */
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#define USB2_OC_TIMSET_INIT 0x000209ab
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/******* HSUSB registers (original offset is +0x100) *******/
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#define HSUSB_LPSTS 0x02
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#define HSUSB_UGCTRL2 0x84
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/* Low Power Status register (LPSTS) */
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#define HSUSB_LPSTS_SUSPM 0x4000
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/* USB General control register 2 (UGCTRL2) */
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#define HSUSB_UGCTRL2_MASK 0x00000031 /* bit[31:6] should be 0 */
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#define HSUSB_UGCTRL2_USB0SEL 0x00000030
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#define HSUSB_UGCTRL2_USB0SEL_HOST 0x00000010
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#define HSUSB_UGCTRL2_USB0SEL_HS_USB 0x00000020
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#define HSUSB_UGCTRL2_USB0SEL_OTG 0x00000030
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struct rcar_gen3_data {
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void __iomem *base;
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struct clk *clk;
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};
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struct rcar_gen3_chan {
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struct rcar_gen3_data usb2;
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struct rcar_gen3_data hsusb;
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struct phy *phy;
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};
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static int rcar_gen3_phy_usb2_init(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *usb2_base = channel->usb2.base;
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void __iomem *hsusb_base = channel->hsusb.base;
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u32 val;
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/* Initialize USB2 part */
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writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
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writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
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writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
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/* Initialize HSUSB part */
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if (hsusb_base) {
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/* TODO: support "OTG" mode */
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val = readl(hsusb_base + HSUSB_UGCTRL2);
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val = (val & ~HSUSB_UGCTRL2_USB0SEL) |
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HSUSB_UGCTRL2_USB0SEL_HOST;
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writel(val & HSUSB_UGCTRL2_MASK, hsusb_base + HSUSB_UGCTRL2);
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}
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return 0;
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}
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static int rcar_gen3_phy_usb2_exit(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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writel(0, channel->usb2.base + USB2_INT_ENABLE);
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return 0;
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}
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static int rcar_gen3_phy_usb2_power_on(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *usb2_base = channel->usb2.base;
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void __iomem *hsusb_base = channel->hsusb.base;
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u32 val;
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val = readl(usb2_base + USB2_USBCTR);
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val |= USB2_USBCTR_PLL_RST;
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writel(val, usb2_base + USB2_USBCTR);
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val &= ~USB2_USBCTR_PLL_RST;
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writel(val, usb2_base + USB2_USBCTR);
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/*
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* TODO: To reduce power consuming, this driver should set the SUSPM
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* after the PHY detects ID pin as peripheral.
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*/
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if (hsusb_base) {
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/* Power on HSUSB PHY */
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val = readw(hsusb_base + HSUSB_LPSTS);
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val |= HSUSB_LPSTS_SUSPM;
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writew(val, hsusb_base + HSUSB_LPSTS);
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}
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return 0;
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}
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static int rcar_gen3_phy_usb2_power_off(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *hsusb_base = channel->hsusb.base;
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u32 val;
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if (hsusb_base) {
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/* Power off HSUSB PHY */
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val = readw(hsusb_base + HSUSB_LPSTS);
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val &= ~HSUSB_LPSTS_SUSPM;
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writew(val, hsusb_base + HSUSB_LPSTS);
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}
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return 0;
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}
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static struct phy_ops rcar_gen3_phy_usb2_ops = {
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.init = rcar_gen3_phy_usb2_init,
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.exit = rcar_gen3_phy_usb2_exit,
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.power_on = rcar_gen3_phy_usb2_power_on,
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.power_off = rcar_gen3_phy_usb2_power_off,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
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{ .compatible = "renesas,usb2-phy-r8a7795" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
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static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rcar_gen3_chan *channel;
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struct phy_provider *provider;
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struct resource *res;
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if (!dev->of_node) {
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dev_err(dev, "This driver needs device tree\n");
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return -EINVAL;
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}
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channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
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if (!channel)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usb2_host");
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channel->usb2.base = devm_ioremap_resource(dev, res);
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if (IS_ERR(channel->usb2.base))
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return PTR_ERR(channel->usb2.base);
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/* "hsusb" memory resource is optional */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsusb");
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/* To avoid error message by devm_ioremap_resource() */
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if (res) {
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channel->hsusb.base = devm_ioremap_resource(dev, res);
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if (IS_ERR(channel->hsusb.base))
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channel->hsusb.base = NULL;
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}
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/* devm_phy_create() will call pm_runtime_enable(dev); */
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channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops);
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if (IS_ERR(channel->phy)) {
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dev_err(dev, "Failed to create USB2 PHY\n");
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return PTR_ERR(channel->phy);
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}
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phy_set_drvdata(channel->phy, channel);
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(provider))
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dev_err(dev, "Failed to register PHY provider\n");
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return PTR_ERR_OR_ZERO(provider);
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}
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static struct platform_driver rcar_gen3_phy_usb2_driver = {
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.driver = {
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.name = "phy_rcar_gen3_usb2",
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.of_match_table = rcar_gen3_phy_usb2_match_table,
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},
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.probe = rcar_gen3_phy_usb2_probe,
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};
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module_platform_driver(rcar_gen3_phy_usb2_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
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MODULE_AUTHOR("Yoshihiro Shimoda <[email protected]>");

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