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torvaldstorvalds
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Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/r600: fix possible NULL pointer derefernce drm/radeon/kms: add quirk for ASUS HD 3600 board include/linux/vgaarb.h: add missing part of include guard drm/nouveau: Fix crashes during fbcon init on single head cards. drm/nouveau: fix pcirom vbios shadow breakage from acpi rom patch drm/radeon/kms: fix shared ddc harder drm/i915: enable low power render writes on GEN3 hardware. drm/i915: Define MI_ARB_STATE bits vmwgfx: return -EFAULT if copy_to_user fails fb: handle allocation failure in alloc_apertures() drm: radeon: check kzalloc() result drm/ttm: Fix build on architectures without AGP drm/radeon/kms: fix gtt MC base alignment on rs4xx/rs690/rs740 asics drm/radeon/kms: fix possible mis-detection of sideport on rs690/rs740 drm/radeon/kms: fix legacy tv-out pal mode
2 parents e095937 + c42750b commit f4b23cc

22 files changed

+142
-49
lines changed

‎drivers/gpu/drm/i915/i915_gem.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4742,6 +4742,16 @@ i915_gem_load(struct drm_device *dev)
47424742
list_add(&dev_priv->mm.shrink_list, &shrink_list);
47434743
spin_unlock(&shrink_list_lock);
47444744

4745+
/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4746+
if (IS_GEN3(dev)) {
4747+
u32 tmp = I915_READ(MI_ARB_STATE);
4748+
if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4749+
/* arb state is a masked write, so set bit + bit in mask */
4750+
tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4751+
I915_WRITE(MI_ARB_STATE, tmp);
4752+
}
4753+
}
4754+
47454755
/* Old X drivers will take 0-2 for front, back, depth buffers */
47464756
if (!drm_core_check_feature(dev, DRIVER_MODESET))
47474757
dev_priv->fence_reg_start = 3;

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -359,6 +359,70 @@
359359
#define LM_BURST_LENGTH 0x00000700
360360
#define LM_FIFO_WATERMARK 0x0000001F
361361
#define MI_ARB_STATE 0x020e4 /* 915+ only */
362+
#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
363+
364+
/* Make render/texture TLB fetches lower priorty than associated data
365+
* fetches. This is not turned on by default
366+
*/
367+
#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
368+
369+
/* Isoch request wait on GTT enable (Display A/B/C streams).
370+
* Make isoch requests stall on the TLB update. May cause
371+
* display underruns (test mode only)
372+
*/
373+
#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
374+
375+
/* Block grant count for isoch requests when block count is
376+
* set to a finite value.
377+
*/
378+
#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
379+
#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
380+
#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
381+
#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
382+
#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
383+
384+
/* Enable render writes to complete in C2/C3/C4 power states.
385+
* If this isn't enabled, render writes are prevented in low
386+
* power states. That seems bad to me.
387+
*/
388+
#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
389+
390+
/* This acknowledges an async flip immediately instead
391+
* of waiting for 2TLB fetches.
392+
*/
393+
#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
394+
395+
/* Enables non-sequential data reads through arbiter
396+
*/
397+
#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
398+
399+
/* Disable FSB snooping of cacheable write cycles from binner/render
400+
* command stream
401+
*/
402+
#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
403+
404+
/* Arbiter time slice for non-isoch streams */
405+
#define MI_ARB_TIME_SLICE_MASK (7 << 5)
406+
#define MI_ARB_TIME_SLICE_1 (0 << 5)
407+
#define MI_ARB_TIME_SLICE_2 (1 << 5)
408+
#define MI_ARB_TIME_SLICE_4 (2 << 5)
409+
#define MI_ARB_TIME_SLICE_6 (3 << 5)
410+
#define MI_ARB_TIME_SLICE_8 (4 << 5)
411+
#define MI_ARB_TIME_SLICE_10 (5 << 5)
412+
#define MI_ARB_TIME_SLICE_14 (6 << 5)
413+
#define MI_ARB_TIME_SLICE_16 (7 << 5)
414+
415+
/* Low priority grace period page size */
416+
#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
417+
#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
418+
419+
/* Disable display A/B trickle feed */
420+
#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
421+
422+
/* Set display plane priority */
423+
#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
424+
#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
425+
362426
#define CACHE_MODE_0 0x02120 /* 915+ only */
363427
#define CM0_MASK_SHIFT 16
364428
#define CM0_IZ_OPT_DISABLE (1<<6)

‎drivers/gpu/drm/nouveau/nouveau_bios.c

Lines changed: 9 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -203,36 +203,26 @@ struct methods {
203203
const bool rw;
204204
};
205205

206-
static struct methods nv04_methods[] = {
207-
{ "PROM", load_vbios_prom, false },
208-
{ "PRAMIN", load_vbios_pramin, true },
209-
{ "PCIROM", load_vbios_pci, true },
210-
};
211-
212-
static struct methods nv50_methods[] = {
213-
{ "ACPI", load_vbios_acpi, true },
206+
static struct methods shadow_methods[] = {
214207
{ "PRAMIN", load_vbios_pramin, true },
215208
{ "PROM", load_vbios_prom, false },
216209
{ "PCIROM", load_vbios_pci, true },
210+
{ "ACPI", load_vbios_acpi, true },
217211
};
218212

219-
#define METHODCNT 3
220-
221213
static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
222214
{
223-
struct drm_nouveau_private *dev_priv = dev->dev_private;
224-
struct methods *methods;
225-
int i;
215+
const int nr_methods = ARRAY_SIZE(shadow_methods);
216+
struct methods *methods = shadow_methods;
226217
int testscore = 3;
227-
int scores[METHODCNT];
218+
int scores[nr_methods], i;
228219

229220
if (nouveau_vbios) {
230-
methods = nv04_methods;
231-
for (i = 0; i < METHODCNT; i++)
221+
for (i = 0; i < nr_methods; i++)
232222
if (!strcasecmp(nouveau_vbios, methods[i].desc))
233223
break;
234224

235-
if (i < METHODCNT) {
225+
if (i < nr_methods) {
236226
NV_INFO(dev, "Attempting to use BIOS image from %s\n",
237227
methods[i].desc);
238228

@@ -244,12 +234,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
244234
NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
245235
}
246236

247-
if (dev_priv->card_type < NV_50)
248-
methods = nv04_methods;
249-
else
250-
methods = nv50_methods;
251-
252-
for (i = 0; i < METHODCNT; i++) {
237+
for (i = 0; i < nr_methods; i++) {
253238
NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
254239
methods[i].desc);
255240
data[0] = data[1] = 0; /* avoid reuse of previous image */
@@ -260,7 +245,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
260245
}
261246

262247
while (--testscore > 0) {
263-
for (i = 0; i < METHODCNT; i++) {
248+
for (i = 0; i < nr_methods; i++) {
264249
if (scores[i] == testscore) {
265250
NV_TRACE(dev, "Using BIOS image from %s\n",
266251
methods[i].desc);

‎drivers/gpu/drm/nouveau/nouveau_fbcon.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -387,7 +387,8 @@ int nouveau_fbcon_init(struct drm_device *dev)
387387
dev_priv->nfbdev = nfbdev;
388388
nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs;
389389

390-
ret = drm_fb_helper_init(dev, &nfbdev->helper, 2, 4);
390+
ret = drm_fb_helper_init(dev, &nfbdev->helper,
391+
nv_two_heads(dev) ? 2 : 1, 4);
391392
if (ret) {
392393
kfree(nfbdev);
393394
return ret;

‎drivers/gpu/drm/radeon/r100.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2354,6 +2354,7 @@ void r100_mc_init(struct radeon_device *rdev)
23542354
if (rdev->flags & RADEON_IS_IGP)
23552355
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
23562356
radeon_vram_location(rdev, &rdev->mc, base);
2357+
rdev->mc.gtt_base_align = 0;
23572358
if (!(rdev->flags & RADEON_IS_AGP))
23582359
radeon_gtt_location(rdev, &rdev->mc);
23592360
radeon_update_bandwidth_info(rdev);

‎drivers/gpu/drm/radeon/r300.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -481,6 +481,7 @@ void r300_mc_init(struct radeon_device *rdev)
481481
if (rdev->flags & RADEON_IS_IGP)
482482
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
483483
radeon_vram_location(rdev, &rdev->mc, base);
484+
rdev->mc.gtt_base_align = 0;
484485
if (!(rdev->flags & RADEON_IS_AGP))
485486
radeon_gtt_location(rdev, &rdev->mc);
486487
radeon_update_bandwidth_info(rdev);
@@ -1176,6 +1177,8 @@ int r300_cs_parse(struct radeon_cs_parser *p)
11761177
int r;
11771178

11781179
track = kzalloc(sizeof(*track), GFP_KERNEL);
1180+
if (track == NULL)
1181+
return -ENOMEM;
11791182
r100_cs_track_clear(p->rdev, track);
11801183
p->track = track;
11811184
do {

‎drivers/gpu/drm/radeon/r520.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,7 @@ void r520_mc_init(struct radeon_device *rdev)
125125
r520_vram_get_type(rdev);
126126
r100_vram_init_sizes(rdev);
127127
radeon_vram_location(rdev, &rdev->mc, 0);
128+
rdev->mc.gtt_base_align = 0;
128129
if (!(rdev->flags & RADEON_IS_AGP))
129130
radeon_gtt_location(rdev, &rdev->mc);
130131
radeon_update_bandwidth_info(rdev);

‎drivers/gpu/drm/radeon/r600.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1179,6 +1179,7 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
11791179
if (rdev->flags & RADEON_IS_IGP)
11801180
base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
11811181
radeon_vram_location(rdev, &rdev->mc, base);
1182+
rdev->mc.gtt_base_align = 0;
11821183
radeon_gtt_location(rdev, mc);
11831184
}
11841185
}

‎drivers/gpu/drm/radeon/r600_blit.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -538,9 +538,12 @@ int
538538
r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
539539
{
540540
drm_radeon_private_t *dev_priv = dev->dev_private;
541+
int ret;
541542
DRM_DEBUG("\n");
542543

543-
r600_nomm_get_vb(dev);
544+
ret = r600_nomm_get_vb(dev);
545+
if (ret)
546+
return ret;
544547

545548
dev_priv->blit_vb->file_priv = file_priv;
546549

‎drivers/gpu/drm/radeon/radeon.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -351,6 +351,7 @@ struct radeon_mc {
351351
int vram_mtrr;
352352
bool vram_is_ddr;
353353
bool igp_sideport_enabled;
354+
u64 gtt_base_align;
354355
};
355356

356357
bool radeon_combios_sideport_present(struct radeon_device *rdev);

‎drivers/gpu/drm/radeon/radeon_atombios.c

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -280,6 +280,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
280280
}
281281
}
282282

283+
/* ASUS HD 3600 board lists the DVI port as HDMI */
284+
if ((dev->pdev->device == 0x9598) &&
285+
(dev->pdev->subsystem_vendor == 0x1043) &&
286+
(dev->pdev->subsystem_device == 0x01e4)) {
287+
if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
288+
*connector_type = DRM_MODE_CONNECTOR_DVII;
289+
}
290+
}
291+
283292
/* ASUS HD 3450 board lists the DVI port as HDMI */
284293
if ((dev->pdev->device == 0x95C5) &&
285294
(dev->pdev->subsystem_vendor == 0x1043) &&
@@ -1029,8 +1038,15 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
10291038
data_offset);
10301039
switch (crev) {
10311040
case 1:
1032-
if (igp_info->info.ucMemoryType & 0xf0)
1033-
return true;
1041+
/* AMD IGPS */
1042+
if ((rdev->family == CHIP_RS690) ||
1043+
(rdev->family == CHIP_RS740)) {
1044+
if (igp_info->info.ulBootUpMemoryClock)
1045+
return true;
1046+
} else {
1047+
if (igp_info->info.ucMemoryType & 0xf0)
1048+
return true;
1049+
}
10341050
break;
10351051
case 2:
10361052
if (igp_info->info_2.ucMemoryType & 0x0f)

‎drivers/gpu/drm/radeon/radeon_connectors.c

Lines changed: 9 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -771,14 +771,14 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
771771
} else
772772
ret = connector_status_connected;
773773

774-
/* multiple connectors on the same encoder with the same ddc line
775-
* This tends to be HDMI and DVI on the same encoder with the
776-
* same ddc line. If the edid says HDMI, consider the HDMI port
777-
* connected and the DVI port disconnected. If the edid doesn't
778-
* say HDMI, vice versa.
774+
/* This gets complicated. We have boards with VGA + HDMI with a
775+
* shared DDC line and we have boards with DVI-D + HDMI with a shared
776+
* DDC line. The latter is more complex because with DVI<->HDMI adapters
777+
* you don't really know what's connected to which port as both are digital.
779778
*/
780779
if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
781780
struct drm_device *dev = connector->dev;
781+
struct radeon_device *rdev = dev->dev_private;
782782
struct drm_connector *list_connector;
783783
struct radeon_connector *list_radeon_connector;
784784
list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
@@ -788,15 +788,10 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
788788
if (list_radeon_connector->shared_ddc &&
789789
(list_radeon_connector->ddc_bus->rec.i2c_id ==
790790
radeon_connector->ddc_bus->rec.i2c_id)) {
791-
if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
792-
if (connector->connector_type == DRM_MODE_CONNECTOR_DVID) {
793-
kfree(radeon_connector->edid);
794-
radeon_connector->edid = NULL;
795-
ret = connector_status_disconnected;
796-
}
797-
} else {
798-
if ((connector->connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
799-
(connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
791+
/* cases where both connectors are digital */
792+
if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
793+
/* hpd is our only option in this case */
794+
if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
800795
kfree(radeon_connector->edid);
801796
radeon_connector->edid = NULL;
802797
ret = connector_status_disconnected;

‎drivers/gpu/drm/radeon/radeon_device.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -226,20 +226,20 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
226226
{
227227
u64 size_af, size_bf;
228228

229-
size_af = 0xFFFFFFFF - mc->vram_end;
230-
size_bf = mc->vram_start;
229+
size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
230+
size_bf = mc->vram_start & ~mc->gtt_base_align;
231231
if (size_bf > size_af) {
232232
if (mc->gtt_size > size_bf) {
233233
dev_warn(rdev->dev, "limiting GTT\n");
234234
mc->gtt_size = size_bf;
235235
}
236-
mc->gtt_start = mc->vram_start - mc->gtt_size;
236+
mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
237237
} else {
238238
if (mc->gtt_size > size_af) {
239239
dev_warn(rdev->dev, "limiting GTT\n");
240240
mc->gtt_size = size_af;
241241
}
242-
mc->gtt_start = mc->vram_end + 1;
242+
mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
243243
}
244244
mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
245245
dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",

‎drivers/gpu/drm/radeon/radeon_legacy_tv.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -642,8 +642,8 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
642642
}
643643
flicker_removal = (tmp + 500) / 1000;
644644

645-
if (flicker_removal < 2)
646-
flicker_removal = 2;
645+
if (flicker_removal < 3)
646+
flicker_removal = 3;
647647
for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
648648
if (flicker_removal == SLOPE_limit[i])
649649
break;

‎drivers/gpu/drm/radeon/rs400.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,9 @@ void rs400_gart_adjust_size(struct radeon_device *rdev)
5757
}
5858
if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
5959
/* FIXME: RS400 & RS480 seems to have issue with GART size
60-
* if 4G of system memory (needs more testing) */
60+
* if 4G of system memory (needs more testing)
61+
*/
62+
/* XXX is this still an issue with proper alignment? */
6163
rdev->mc.gtt_size = 32 * 1024 * 1024;
6264
DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
6365
}
@@ -263,6 +265,7 @@ void rs400_mc_init(struct radeon_device *rdev)
263265
r100_vram_init_sizes(rdev);
264266
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
265267
radeon_vram_location(rdev, &rdev->mc, base);
268+
rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
266269
radeon_gtt_location(rdev, &rdev->mc);
267270
radeon_update_bandwidth_info(rdev);
268271
}

‎drivers/gpu/drm/radeon/rs600.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -698,6 +698,7 @@ void rs600_mc_init(struct radeon_device *rdev)
698698
base = G_000004_MC_FB_START(base) << 16;
699699
rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
700700
radeon_vram_location(rdev, &rdev->mc, base);
701+
rdev->mc.gtt_base_align = 0;
701702
radeon_gtt_location(rdev, &rdev->mc);
702703
radeon_update_bandwidth_info(rdev);
703704
}

‎drivers/gpu/drm/radeon/rs690.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -162,6 +162,7 @@ void rs690_mc_init(struct radeon_device *rdev)
162162
rs690_pm_info(rdev);
163163
rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
164164
radeon_vram_location(rdev, &rdev->mc, base);
165+
rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
165166
radeon_gtt_location(rdev, &rdev->mc);
166167
radeon_update_bandwidth_info(rdev);
167168
}

‎drivers/gpu/drm/radeon/rv515.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,7 @@ void rv515_mc_init(struct radeon_device *rdev)
195195
rv515_vram_get_type(rdev);
196196
r100_vram_init_sizes(rdev);
197197
radeon_vram_location(rdev, &rdev->mc, 0);
198+
rdev->mc.gtt_base_align = 0;
198199
if (!(rdev->flags & RADEON_IS_AGP))
199200
radeon_gtt_location(rdev, &rdev->mc);
200201
radeon_update_bandwidth_info(rdev);

‎drivers/gpu/drm/ttm/ttm_page_alloc.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,9 @@
4040
#include <linux/slab.h>
4141

4242
#include <asm/atomic.h>
43+
#ifdef TTM_HAS_AGP
4344
#include <asm/agp.h>
45+
#endif
4446

4547
#include "ttm/ttm_bo_driver.h"
4648
#include "ttm/ttm_page_alloc.h"

‎drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -972,6 +972,7 @@ int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
972972
ret = copy_from_user(rects, user_rects, rects_size);
973973
if (unlikely(ret != 0)) {
974974
DRM_ERROR("Failed to get rects.\n");
975+
ret = -EFAULT;
975976
goto out_free;
976977
}
977978

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