Skip to content

Commit f536579

Browse files
airliedairlied
committed
Merge tag 'drm-fixes-5.3-2019-08-07' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
drm-fixes-5.3-2019-08-07: amdgpu: - Fixes VCN to handle the latest navi10 firmware - Fixes for fan control on navi10 - Properly handle SMU metrics table on navi10 - Fix a resume regression on Stoney amdkfd: - Revert new GWS ioctl. It's not ready. Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents abffeda + 4b3e30e commit f536579

File tree

11 files changed

+138
-94
lines changed

11 files changed

+138
-94
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,6 @@ struct amdgpu_gds {
3232
uint32_t gws_size;
3333
uint32_t oa_size;
3434
uint32_t gds_compute_max_wave_id;
35-
uint32_t vgt_gs_max_wave_id;
3635
};
3736

3837
struct amdgpu_gds_reg_offset {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@
3030
#define AMDGPU_VCN_FIRMWARE_OFFSET 256
3131
#define AMDGPU_VCN_MAX_ENC_RINGS 3
3232

33+
#define VCN_DEC_KMD_CMD 0x80000000
3334
#define VCN_DEC_CMD_FENCE 0x00000000
3435
#define VCN_DEC_CMD_TRAP 0x00000001
3536
#define VCN_DEC_CMD_WRITE_REG 0x00000004

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 1 addition & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4206,15 +4206,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
42064206
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
42074207
u32 header, control = 0;
42084208

4209-
/* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.
4210-
* This resets the wave ID counters. (needed by transform feedback)
4211-
* TODO: This might only be needed on a VMID switch when we change
4212-
* the GDS OA mapping, not sure.
4213-
*/
4214-
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4215-
amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);
4216-
amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);
4217-
42184209
if (ib->flags & AMDGPU_IB_FLAG_CE)
42194210
header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
42204211
else
@@ -4961,7 +4952,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
49614952
5 + /* HDP_INVL */
49624953
8 + 8 + /* FENCE x2 */
49634954
2, /* SWITCH_BUFFER */
4964-
.emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_gfx */
4955+
.emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
49654956
.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
49664957
.emit_fence = gfx_v10_0_ring_emit_fence,
49674958
.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
@@ -5112,7 +5103,6 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
51125103
default:
51135104
adev->gds.gds_size = 0x10000;
51145105
adev->gds.gds_compute_max_wave_id = 0x4ff;
5115-
adev->gds.vgt_gs_max_wave_id = 0x3ff;
51165106
break;
51175107
}
51185108

‎drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1321,6 +1321,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
13211321
return 0;
13221322
}
13231323

1324+
static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
1325+
{
1326+
int r;
1327+
1328+
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1329+
if (unlikely(r != 0))
1330+
return r;
1331+
1332+
r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1333+
AMDGPU_GEM_DOMAIN_VRAM);
1334+
if (!r)
1335+
adev->gfx.rlc.clear_state_gpu_addr =
1336+
amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1337+
1338+
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1339+
1340+
return r;
1341+
}
1342+
1343+
static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
1344+
{
1345+
int r;
1346+
1347+
if (!adev->gfx.rlc.clear_state_obj)
1348+
return;
1349+
1350+
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1351+
if (likely(r == 0)) {
1352+
amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1353+
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1354+
}
1355+
}
1356+
13241357
static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
13251358
{
13261359
amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
@@ -4785,6 +4818,10 @@ static int gfx_v8_0_hw_init(void *handle)
47854818
gfx_v8_0_init_golden_registers(adev);
47864819
gfx_v8_0_constants_init(adev);
47874820

4821+
r = gfx_v8_0_csb_vram_pin(adev);
4822+
if (r)
4823+
return r;
4824+
47884825
r = adev->gfx.rlc.funcs->resume(adev);
47894826
if (r)
47904827
return r;
@@ -4901,6 +4938,9 @@ static int gfx_v8_0_hw_fini(void *handle)
49014938
else
49024939
pr_err("rlc is busy, skip halt rlc\n");
49034940
amdgpu_gfx_rlc_exit_safe_mode(adev);
4941+
4942+
gfx_v8_0_csb_vram_unpin(adev);
4943+
49044944
return 0;
49054945
}
49064946

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

Lines changed: 37 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1485,7 +1485,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
14851485
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
14861486
amdgpu_ring_write(ring, 0);
14871487
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
1488-
amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1488+
amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
14891489
}
14901490

14911491
/**
@@ -1498,7 +1498,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
14981498
static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
14991499
{
15001500
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
1501-
amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1501+
amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
15021502
}
15031503

15041504
/**
@@ -1543,7 +1543,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
15431543
amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
15441544

15451545
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
1546-
amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1546+
amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
15471547

15481548
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
15491549
amdgpu_ring_write(ring, 0);
@@ -1553,7 +1553,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
15531553

15541554
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
15551555

1556-
amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1556+
amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
15571557
}
15581558

15591559
/**
@@ -1597,7 +1597,7 @@ static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
15971597

15981598
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
15991599

1600-
amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1600+
amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
16011601
}
16021602

16031603
static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
@@ -1626,7 +1626,7 @@ static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
16261626

16271627
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
16281628

1629-
amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1629+
amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
16301630
}
16311631

16321632
/**
@@ -2079,6 +2079,36 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
20792079
return 0;
20802080
}
20812081

2082+
static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
2083+
{
2084+
struct amdgpu_device *adev = ring->adev;
2085+
uint32_t tmp = 0;
2086+
unsigned i;
2087+
int r;
2088+
2089+
WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
2090+
r = amdgpu_ring_alloc(ring, 4);
2091+
if (r)
2092+
return r;
2093+
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
2094+
amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
2095+
amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
2096+
amdgpu_ring_write(ring, 0xDEADBEEF);
2097+
amdgpu_ring_commit(ring);
2098+
for (i = 0; i < adev->usec_timeout; i++) {
2099+
tmp = RREG32(adev->vcn.external.scratch9);
2100+
if (tmp == 0xDEADBEEF)
2101+
break;
2102+
DRM_UDELAY(1);
2103+
}
2104+
2105+
if (i >= adev->usec_timeout)
2106+
r = -ETIMEDOUT;
2107+
2108+
return r;
2109+
}
2110+
2111+
20822112
static int vcn_v2_0_set_powergating_state(void *handle,
20832113
enum amd_powergating_state state)
20842114
{
@@ -2142,7 +2172,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
21422172
.emit_ib = vcn_v2_0_dec_ring_emit_ib,
21432173
.emit_fence = vcn_v2_0_dec_ring_emit_fence,
21442174
.emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
2145-
.test_ring = amdgpu_vcn_dec_ring_test_ring,
2175+
.test_ring = vcn_v2_0_dec_ring_test_ring,
21462176
.test_ib = amdgpu_vcn_dec_ring_test_ib,
21472177
.insert_nop = vcn_v2_0_dec_ring_insert_nop,
21482178
.insert_start = vcn_v2_0_dec_ring_insert_start,

‎drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

Lines changed: 0 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1567,32 +1567,6 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
15671567
return err;
15681568
}
15691569

1570-
static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1571-
struct kfd_process *p, void *data)
1572-
{
1573-
int retval;
1574-
struct kfd_ioctl_alloc_queue_gws_args *args = data;
1575-
struct kfd_dev *dev;
1576-
1577-
if (!hws_gws_support)
1578-
return -ENODEV;
1579-
1580-
dev = kfd_device_by_id(args->gpu_id);
1581-
if (!dev) {
1582-
pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
1583-
return -ENODEV;
1584-
}
1585-
if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
1586-
return -ENODEV;
1587-
1588-
mutex_lock(&p->mutex);
1589-
retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1590-
mutex_unlock(&p->mutex);
1591-
1592-
args->first_gws = 0;
1593-
return retval;
1594-
}
1595-
15961570
static int kfd_ioctl_get_dmabuf_info(struct file *filep,
15971571
struct kfd_process *p, void *data)
15981572
{
@@ -1795,8 +1769,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
17951769
AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
17961770
kfd_ioctl_import_dmabuf, 0),
17971771

1798-
AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
1799-
kfd_ioctl_alloc_queue_gws, 0),
18001772
};
18011773

18021774
#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)

‎drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -315,6 +315,8 @@ int smu_get_power_num_states(struct smu_context *smu,
315315
int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
316316
void *data, uint32_t *size)
317317
{
318+
struct smu_power_context *smu_power = &smu->smu_power;
319+
struct smu_power_gate *power_gate = &smu_power->power_gate;
318320
int ret = 0;
319321

320322
switch (sensor) {
@@ -339,7 +341,7 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
339341
*size = 4;
340342
break;
341343
case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
342-
*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT) ? 1 : 0;
344+
*(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
343345
*size = 4;
344346
break;
345347
default:

‎drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -451,6 +451,7 @@ struct smu_dpm_context {
451451
struct smu_power_gate {
452452
bool uvd_gated;
453453
bool vce_gated;
454+
bool vcn_gated;
454455
};
455456

456457
struct smu_power_context {

0 commit comments

Comments
 (0)