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kimphillamdsuryasaimadhu
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perf/amd/uncore: Replace manual sampling check with CAP_NO_INTERRUPT flag
Enable the sampling check in kernel/events/core.c::perf_event_open(), which returns the more appropriate -EOPNOTSUPP. BEFORE: $ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true Error: The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (l3_request_g1.caching_l3_cache_accesses). /bin/dmesg | grep -i perf may provide additional information. With nothing relevant in dmesg. AFTER: $ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true Error: l3_request_g1.caching_l3_cache_accesses: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat' Fixes: c43ca50 ("perf/x86/amd: Add support for AMD NB and L2I "uncore" counters") Signed-off-by: Kim Phillips <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Acked-by: Peter Zijlstra <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected]
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arch/x86/events/amd/uncore.c

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -190,15 +190,12 @@ static int amd_uncore_event_init(struct perf_event *event)
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/*
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* NB and Last level cache counters (MSRs) are shared across all cores
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* that share the same NB / Last level cache. Interrupts can be directed
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* to a single target core, however, event counts generated by processes
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* running on other cores cannot be masked out. So we do not support
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* sampling and per-thread events.
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* that share the same NB / Last level cache. On family 16h and below,
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* Interrupts can be directed to a single target core, however, event
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* counts generated by processes running on other cores cannot be masked
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* out. So we do not support sampling and per-thread events via
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* CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts:
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*/
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if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
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return -EINVAL;
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/* and we do not enable counter overflow interrupts */
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hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
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hwc->idx = -1;
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@@ -306,7 +303,7 @@ static struct pmu amd_nb_pmu = {
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.start = amd_uncore_start,
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.stop = amd_uncore_stop,
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.read = amd_uncore_read,
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
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};
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static struct pmu amd_llc_pmu = {
@@ -317,7 +314,7 @@ static struct pmu amd_llc_pmu = {
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.start = amd_uncore_start,
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.stop = amd_uncore_stop,
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.read = amd_uncore_read,
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
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};
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static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)

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