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arm64: dts: juno: add information about L1 and L2 caches
Commit a8d4636 ("arm64: cacheinfo: Remove CCSIDR-based cache information probing") removed mechanism to extract cache information based on CCSIDR register as the architecture explicitly states no inference about the actual sizes of caches based on CCSIDR registers. Commit 9a80243 ("arm64: cacheinfo: add support to override cache levels via device tree") had already provided options to override cache information from the device tree. This patch adds the information about L1 and L2 caches on all variants of Juno platform. Cc: Will Deacon <[email protected]> Cc: Liviu Dudau <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
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‎arch/arm64/boot/dts/arm/juno-r1.dts

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,12 @@
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
92+
i-cache-size = <0xc000>;
93+
i-cache-line-size = <64>;
94+
i-cache-sets = <256>;
95+
d-cache-size = <0x8000>;
96+
d-cache-line-size = <64>;
97+
d-cache-sets = <256>;
9298
next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -100,6 +106,12 @@
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reg = <0x0 0x1>;
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device_type = "cpu";
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enable-method = "psci";
109+
i-cache-size = <0xc000>;
110+
i-cache-line-size = <64>;
111+
i-cache-sets = <256>;
112+
d-cache-size = <0x8000>;
113+
d-cache-line-size = <64>;
114+
d-cache-sets = <256>;
103115
next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -111,6 +123,12 @@
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
126+
i-cache-size = <0x8000>;
127+
i-cache-line-size = <64>;
128+
i-cache-sets = <256>;
129+
d-cache-size = <0x8000>;
130+
d-cache-line-size = <64>;
131+
d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -122,6 +140,12 @@
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reg = <0x0 0x101>;
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device_type = "cpu";
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enable-method = "psci";
143+
i-cache-size = <0x8000>;
144+
i-cache-line-size = <64>;
145+
i-cache-sets = <256>;
146+
d-cache-size = <0x8000>;
147+
d-cache-line-size = <64>;
148+
d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -133,6 +157,12 @@
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reg = <0x0 0x102>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
161+
i-cache-line-size = <64>;
162+
i-cache-sets = <256>;
163+
d-cache-size = <0x8000>;
164+
d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -144,6 +174,12 @@
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reg = <0x0 0x103>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
178+
i-cache-line-size = <64>;
179+
i-cache-sets = <256>;
180+
d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -152,10 +188,16 @@
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A57_L2: l2-cache0 {
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compatible = "cache";
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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};
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A53_L2: l2-cache1 {
158197
compatible = "cache";
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cache-size = <0x100000>;
199+
cache-line-size = <64>;
200+
cache-sets = <1024>;
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};
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};
161203

‎arch/arm64/boot/dts/arm/juno-r2.dts

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,12 @@
8989
reg = <0x0 0x0>;
9090
device_type = "cpu";
9191
enable-method = "psci";
92+
i-cache-size = <0xc000>;
93+
i-cache-line-size = <64>;
94+
i-cache-sets = <256>;
95+
d-cache-size = <0x8000>;
96+
d-cache-line-size = <64>;
97+
d-cache-sets = <256>;
9298
next-level-cache = <&A72_L2>;
9399
clocks = <&scpi_dvfs 0>;
94100
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -100,6 +106,12 @@
100106
reg = <0x0 0x1>;
101107
device_type = "cpu";
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enable-method = "psci";
109+
i-cache-size = <0xc000>;
110+
i-cache-line-size = <64>;
111+
i-cache-sets = <256>;
112+
d-cache-size = <0x8000>;
113+
d-cache-line-size = <64>;
114+
d-cache-sets = <256>;
103115
next-level-cache = <&A72_L2>;
104116
clocks = <&scpi_dvfs 0>;
105117
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -111,6 +123,12 @@
111123
reg = <0x0 0x100>;
112124
device_type = "cpu";
113125
enable-method = "psci";
126+
i-cache-size = <0x8000>;
127+
i-cache-line-size = <64>;
128+
i-cache-sets = <256>;
129+
d-cache-size = <0x8000>;
130+
d-cache-line-size = <64>;
131+
d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
116134
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -122,6 +140,12 @@
122140
reg = <0x0 0x101>;
123141
device_type = "cpu";
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enable-method = "psci";
143+
i-cache-size = <0x8000>;
144+
i-cache-line-size = <64>;
145+
i-cache-sets = <256>;
146+
d-cache-size = <0x8000>;
147+
d-cache-line-size = <64>;
148+
d-cache-sets = <128>;
125149
next-level-cache = <&A53_L2>;
126150
clocks = <&scpi_dvfs 1>;
127151
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -133,6 +157,12 @@
133157
reg = <0x0 0x102>;
134158
device_type = "cpu";
135159
enable-method = "psci";
160+
i-cache-size = <0x8000>;
161+
i-cache-line-size = <64>;
162+
i-cache-sets = <256>;
163+
d-cache-size = <0x8000>;
164+
d-cache-line-size = <64>;
165+
d-cache-sets = <128>;
136166
next-level-cache = <&A53_L2>;
137167
clocks = <&scpi_dvfs 1>;
138168
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -144,6 +174,12 @@
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reg = <0x0 0x103>;
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device_type = "cpu";
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enable-method = "psci";
177+
i-cache-size = <0x8000>;
178+
i-cache-line-size = <64>;
179+
i-cache-sets = <256>;
180+
d-cache-size = <0x8000>;
181+
d-cache-line-size = <64>;
182+
d-cache-sets = <128>;
147183
next-level-cache = <&A53_L2>;
148184
clocks = <&scpi_dvfs 1>;
149185
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -152,10 +188,16 @@
152188

153189
A72_L2: l2-cache0 {
154190
compatible = "cache";
191+
cache-size = <0x200000>;
192+
cache-line-size = <64>;
193+
cache-sets = <2048>;
155194
};
156195

157196
A53_L2: l2-cache1 {
158197
compatible = "cache";
198+
cache-size = <0x100000>;
199+
cache-line-size = <64>;
200+
cache-sets = <1024>;
159201
};
160202
};
161203

‎arch/arm64/boot/dts/arm/juno.dts

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,12 @@
8888
reg = <0x0 0x0>;
8989
device_type = "cpu";
9090
enable-method = "psci";
91+
i-cache-size = <0xc000>;
92+
i-cache-line-size = <64>;
93+
i-cache-sets = <256>;
94+
d-cache-size = <0x8000>;
95+
d-cache-line-size = <64>;
96+
d-cache-sets = <256>;
9197
next-level-cache = <&A57_L2>;
9298
clocks = <&scpi_dvfs 0>;
9399
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -99,6 +105,12 @@
99105
reg = <0x0 0x1>;
100106
device_type = "cpu";
101107
enable-method = "psci";
108+
i-cache-size = <0xc000>;
109+
i-cache-line-size = <64>;
110+
i-cache-sets = <256>;
111+
d-cache-size = <0x8000>;
112+
d-cache-line-size = <64>;
113+
d-cache-sets = <256>;
102114
next-level-cache = <&A57_L2>;
103115
clocks = <&scpi_dvfs 0>;
104116
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -110,6 +122,12 @@
110122
reg = <0x0 0x100>;
111123
device_type = "cpu";
112124
enable-method = "psci";
125+
i-cache-size = <0x8000>;
126+
i-cache-line-size = <64>;
127+
i-cache-sets = <256>;
128+
d-cache-size = <0x8000>;
129+
d-cache-line-size = <64>;
130+
d-cache-sets = <128>;
113131
next-level-cache = <&A53_L2>;
114132
clocks = <&scpi_dvfs 1>;
115133
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -121,6 +139,12 @@
121139
reg = <0x0 0x101>;
122140
device_type = "cpu";
123141
enable-method = "psci";
142+
i-cache-size = <0x8000>;
143+
i-cache-line-size = <64>;
144+
i-cache-sets = <256>;
145+
d-cache-size = <0x8000>;
146+
d-cache-line-size = <64>;
147+
d-cache-sets = <128>;
124148
next-level-cache = <&A53_L2>;
125149
clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -132,6 +156,12 @@
132156
reg = <0x0 0x102>;
133157
device_type = "cpu";
134158
enable-method = "psci";
159+
i-cache-size = <0x8000>;
160+
i-cache-line-size = <64>;
161+
i-cache-sets = <256>;
162+
d-cache-size = <0x8000>;
163+
d-cache-line-size = <64>;
164+
d-cache-sets = <128>;
135165
next-level-cache = <&A53_L2>;
136166
clocks = <&scpi_dvfs 1>;
137167
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -143,6 +173,12 @@
143173
reg = <0x0 0x103>;
144174
device_type = "cpu";
145175
enable-method = "psci";
176+
i-cache-size = <0x8000>;
177+
i-cache-line-size = <64>;
178+
i-cache-sets = <256>;
179+
d-cache-size = <0x8000>;
180+
d-cache-line-size = <64>;
181+
d-cache-sets = <128>;
146182
next-level-cache = <&A53_L2>;
147183
clocks = <&scpi_dvfs 1>;
148184
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -151,10 +187,16 @@
151187

152188
A57_L2: l2-cache0 {
153189
compatible = "cache";
190+
cache-size = <0x200000>;
191+
cache-line-size = <64>;
192+
cache-sets = <2048>;
154193
};
155194

156195
A53_L2: l2-cache1 {
157196
compatible = "cache";
197+
cache-size = <0x100000>;
198+
cache-line-size = <64>;
199+
cache-sets = <1024>;
158200
};
159201
};
160202

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