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Andrea della Portaffainelli
Andrea della Porta
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ffainelli
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arm64: dts: broadcom: Add minimal support for Raspberry Pi 5
The BCM2712 SoC family can be found on Raspberry Pi 5. Add minimal SoC and board (Rpi5 specific) dts file to be able to boot from SD card and use console on debug UART. Signed-off-by: Andrea della Porta <[email protected]> Reviewed-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/874589f6c621036620cca944986e5be7238b4784.1717061147.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <[email protected]>
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‎arch/arm64/boot/dts/broadcom/Makefile

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@@ -6,6 +6,7 @@ DTC_FLAGS := -@
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
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bcm2711-rpi-4-b.dtb \
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bcm2711-rpi-cm4-io.dtb \
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bcm2712-rpi-5-b.dtb \
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bcm2837-rpi-3-a-plus.dtb \
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bcm2837-rpi-3-b.dtb \
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bcm2837-rpi-3-b-plus.dtb \

‎arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "bcm2712.dtsi"
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/ {
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compatible = "raspberrypi,5-model-b", "brcm,bcm2712";
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model = "Raspberry Pi 5";
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aliases {
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serial10 = &uart10;
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};
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chosen: chosen {
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stdout-path = "serial10:115200n8";
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};
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/* Will be filled by the bootloader */
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memory@0 {
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device_type = "memory";
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reg = <0 0 0 0x28000000>;
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};
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sd_io_1v8_reg: sd-io-1v8-reg {
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compatible = "regulator-gpio";
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regulator-name = "vdd-sd-io";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-settling-time-us = <5000>;
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gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>;
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states = <1800000 1>,
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<3300000 0>;
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};
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sd_vcc_reg: sd-vcc-reg {
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compatible = "regulator-fixed";
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regulator-name = "vcc-sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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enable-active-high;
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gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
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};
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};
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/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector
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* labeled "UART", i.e. the interface with the system console.
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*/
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&uart10 {
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status = "okay";
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};
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/* SDIO1 is used to drive the SD card */
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&sdio1 {
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vqmmc-supply = <&sd_io_1v8_reg>;
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vmmc-supply = <&sd_vcc_reg>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-ddr50;
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sd-uhs-sdr104;
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};

‎arch/arm64/boot/dts/broadcom/bcm2712.dtsi

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "brcm,bcm2712";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gicv2>;
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clocks {
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/* The oscillator is the root of the clock tree. */
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clk_osc: clk-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "osc";
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clock-frequency = <54000000>;
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};
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clk_vpu: clk-vpu {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <750000000>;
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clock-output-names = "vpu-clock";
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};
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clk_uart: clk-uart {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <9216000>;
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clock-output-names = "uart-clock";
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};
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clk_emmc2: clk-emmc2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "emmc2-clock";
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};
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Source for L1 d/i cache-line-size, cache-sets, cache-size
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* https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en
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* Source for L2 cache-line-size and cache-sets:
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* https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en
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* and for cache-size:
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* https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
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*/
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x000>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l0>;
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l2_cache_l0: l2-cache-l0 {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <128>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x100>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l1>;
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l2_cache_l1: l2-cache-l1 {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <128>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x200>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l2>;
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l2_cache_l2: l2-cache-l2 {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <128>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x300>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l3>;
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l2_cache_l3: l2-cache-l3 {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <128>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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};
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/* Source for cache-line-size and cache-sets:
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* https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
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* Source for cache-size:
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* https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
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*/
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l3_cache: l3-cache {
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compatible = "cache";
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
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cache-level = <3>;
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cache-unified;
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};
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};
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psci {
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method = "smc";
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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};
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rmem: reserved-memory {
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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atf@0 {
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reg = <0x0 0x0 0x0 0x80000>;
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no-map;
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};
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cma: linux,cma {
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compatible = "shared-dma-pool";
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size = <0x0 0x4000000>; /* 64MB */
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reusable;
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linux,cma-default;
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alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
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};
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};
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soc: soc@107c000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0x10 0x00000000 0x80000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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sdio1: mmc@fff000 {
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compatible = "brcm,bcm2712-sdhci",
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"brcm,sdhci-brcmstb";
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reg = <0x00fff000 0x260>,
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<0x00fff400 0x200>;
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reg-names = "host", "cfg";
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interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_emmc2>;
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clock-names = "sw_sdio";
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mmc-ddr-3_3v;
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};
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system_timer: timer@7c003000 {
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compatible = "brcm,bcm2835-system-timer";
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reg = <0x7c003000 0x1000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <1000000>;
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};
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mailbox: mailbox@7c013880 {
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compatible = "brcm,bcm2835-mbox";
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reg = <0x7c013880 0x40>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <0>;
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};
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local_intc: local-intc@7cd00000 {
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compatible = "brcm,bcm2836-l1-intc";
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reg = <0x7cd00000 0x100>;
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};
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uart10: serial@7d001000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x7d001000 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_uart>, <&clk_vpu>;
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clock-names = "uartclk", "apb_pclk";
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arm,primecell-periphid = <0x00241011>;
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status = "disabled";
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};
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interrupt-controller@7d517000 {
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compatible = "brcm,bcm7271-l2-intc";
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reg = <0x7d517000 0x10>;
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interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gio_aon: gpio@7d517c00 {
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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reg = <0x7d517c00 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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brcm,gpio-bank-widths = <17 6>;
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/* The lack of 'interrupt-controller' property here is intended:
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* don't use GIO_AON as an interrupt controller because it will
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* clash with the firmware monitoring the PMIC interrupt via the VPU.
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*/
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};
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gicv2: interrupt-controller@7fff9000 {
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compatible = "arm,gic-400";
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reg = <0x7fff9000 0x1000>,
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<0x7fffa000 0x2000>,
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<0x7fffc000 0x2000>,
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<0x7fffe000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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};

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