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Icenowylinusw
Icenowy
authored and
linusw
committed
pinctrl: sunxi: v3s: introduce support for V3
Introduce the GPIO pins that is only available on V3 (not on V3s) to the V3s pinctrl driver. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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‎drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c

Lines changed: 260 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Allwinner V3s SoCs pinctrl driver.
2+
* Allwinner V3/V3s SoCs pinctrl driver.
33
*
44
* Copyright (C) 2016 Icenowy Zheng <[email protected]>
55
*
@@ -77,6 +77,30 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
7777
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
7878
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
7979
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */
80+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 10),
81+
PINCTRL_SUN8I_V3,
82+
SUNXI_FUNCTION(0x0, "gpio_in"),
83+
SUNXI_FUNCTION(0x1, "gpio_out"),
84+
SUNXI_FUNCTION(0x2, "jtag"), /* MS */
85+
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */
86+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11),
87+
PINCTRL_SUN8I_V3,
88+
SUNXI_FUNCTION(0x0, "gpio_in"),
89+
SUNXI_FUNCTION(0x1, "gpio_out"),
90+
SUNXI_FUNCTION(0x2, "jtag"), /* CK */
91+
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */
92+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12),
93+
PINCTRL_SUN8I_V3,
94+
SUNXI_FUNCTION(0x0, "gpio_in"),
95+
SUNXI_FUNCTION(0x1, "gpio_out"),
96+
SUNXI_FUNCTION(0x2, "jtag"), /* DO */
97+
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */
98+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13),
99+
PINCTRL_SUN8I_V3,
100+
SUNXI_FUNCTION(0x0, "gpio_in"),
101+
SUNXI_FUNCTION(0x1, "gpio_out"),
102+
SUNXI_FUNCTION(0x2, "jtag"), /* DI */
103+
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */
80104
/* Hole */
81105
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
82106
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -98,6 +122,180 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
98122
SUNXI_FUNCTION(0x1, "gpio_out"),
99123
SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */
100124
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
125+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4),
126+
PINCTRL_SUN8I_V3,
127+
SUNXI_FUNCTION(0x0, "gpio_in"),
128+
SUNXI_FUNCTION(0x1, "gpio_out"),
129+
SUNXI_FUNCTION(0x2, "mmc2")), /* D1 */
130+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5),
131+
PINCTRL_SUN8I_V3,
132+
SUNXI_FUNCTION(0x0, "gpio_in"),
133+
SUNXI_FUNCTION(0x1, "gpio_out"),
134+
SUNXI_FUNCTION(0x2, "mmc2")), /* D2 */
135+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6),
136+
PINCTRL_SUN8I_V3,
137+
SUNXI_FUNCTION(0x0, "gpio_in"),
138+
SUNXI_FUNCTION(0x1, "gpio_out"),
139+
SUNXI_FUNCTION(0x2, "mmc2")), /* D3 */
140+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7),
141+
PINCTRL_SUN8I_V3,
142+
SUNXI_FUNCTION(0x0, "gpio_in"),
143+
SUNXI_FUNCTION(0x1, "gpio_out"),
144+
SUNXI_FUNCTION(0x2, "mmc2")), /* D4 */
145+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8),
146+
PINCTRL_SUN8I_V3,
147+
SUNXI_FUNCTION(0x0, "gpio_in"),
148+
SUNXI_FUNCTION(0x1, "gpio_out"),
149+
SUNXI_FUNCTION(0x2, "mmc2")), /* D5 */
150+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9),
151+
PINCTRL_SUN8I_V3,
152+
SUNXI_FUNCTION(0x0, "gpio_in"),
153+
SUNXI_FUNCTION(0x1, "gpio_out"),
154+
SUNXI_FUNCTION(0x2, "mmc2")), /* D6 */
155+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10),
156+
PINCTRL_SUN8I_V3,
157+
SUNXI_FUNCTION(0x0, "gpio_in"),
158+
SUNXI_FUNCTION(0x1, "gpio_out"),
159+
SUNXI_FUNCTION(0x2, "mmc2")), /* D7 */
160+
/* Hole */
161+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0),
162+
PINCTRL_SUN8I_V3,
163+
SUNXI_FUNCTION(0x0, "gpio_in"),
164+
SUNXI_FUNCTION(0x1, "gpio_out"),
165+
SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
166+
SUNXI_FUNCTION(0x4, "emac")), /* RXD3 */
167+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1),
168+
PINCTRL_SUN8I_V3,
169+
SUNXI_FUNCTION(0x0, "gpio_in"),
170+
SUNXI_FUNCTION(0x1, "gpio_out"),
171+
SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
172+
SUNXI_FUNCTION(0x4, "emac")), /* RXD2 */
173+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2),
174+
PINCTRL_SUN8I_V3,
175+
SUNXI_FUNCTION(0x0, "gpio_in"),
176+
SUNXI_FUNCTION(0x1, "gpio_out"),
177+
SUNXI_FUNCTION(0x2, "lcd"), /* D4 */
178+
SUNXI_FUNCTION(0x4, "emac")), /* RXD1 */
179+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 3),
180+
PINCTRL_SUN8I_V3,
181+
SUNXI_FUNCTION(0x0, "gpio_in"),
182+
SUNXI_FUNCTION(0x1, "gpio_out"),
183+
SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
184+
SUNXI_FUNCTION(0x4, "emac")), /* RXD0 */
185+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 4),
186+
PINCTRL_SUN8I_V3,
187+
SUNXI_FUNCTION(0x0, "gpio_in"),
188+
SUNXI_FUNCTION(0x1, "gpio_out"),
189+
SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
190+
SUNXI_FUNCTION(0x4, "emac")), /* RXCK */
191+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 5),
192+
PINCTRL_SUN8I_V3,
193+
SUNXI_FUNCTION(0x0, "gpio_in"),
194+
SUNXI_FUNCTION(0x1, "gpio_out"),
195+
SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
196+
SUNXI_FUNCTION(0x4, "emac")), /* RXCTL/RXDV */
197+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 6),
198+
PINCTRL_SUN8I_V3,
199+
SUNXI_FUNCTION(0x0, "gpio_in"),
200+
SUNXI_FUNCTION(0x1, "gpio_out"),
201+
SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
202+
SUNXI_FUNCTION(0x4, "emac")), /* RXERR */
203+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 7),
204+
PINCTRL_SUN8I_V3,
205+
SUNXI_FUNCTION(0x0, "gpio_in"),
206+
SUNXI_FUNCTION(0x1, "gpio_out"),
207+
SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
208+
SUNXI_FUNCTION(0x4, "emac")), /* TXD3 */
209+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8),
210+
PINCTRL_SUN8I_V3,
211+
SUNXI_FUNCTION(0x0, "gpio_in"),
212+
SUNXI_FUNCTION(0x1, "gpio_out"),
213+
SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
214+
SUNXI_FUNCTION(0x4, "emac")), /* TXD2 */
215+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9),
216+
PINCTRL_SUN8I_V3,
217+
SUNXI_FUNCTION(0x0, "gpio_in"),
218+
SUNXI_FUNCTION(0x1, "gpio_out"),
219+
SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
220+
SUNXI_FUNCTION(0x4, "emac")), /* TXD1 */
221+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10),
222+
PINCTRL_SUN8I_V3,
223+
SUNXI_FUNCTION(0x0, "gpio_in"),
224+
SUNXI_FUNCTION(0x1, "gpio_out"),
225+
SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
226+
SUNXI_FUNCTION(0x4, "emac")), /* TXD0 */
227+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11),
228+
PINCTRL_SUN8I_V3,
229+
SUNXI_FUNCTION(0x0, "gpio_in"),
230+
SUNXI_FUNCTION(0x1, "gpio_out"),
231+
SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
232+
SUNXI_FUNCTION(0x4, "emac")), /* CRS */
233+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12),
234+
PINCTRL_SUN8I_V3,
235+
SUNXI_FUNCTION(0x0, "gpio_in"),
236+
SUNXI_FUNCTION(0x1, "gpio_out"),
237+
SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
238+
SUNXI_FUNCTION(0x3, "lvds"), /* VP0 */
239+
SUNXI_FUNCTION(0x4, "emac")), /* TXCK */
240+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13),
241+
PINCTRL_SUN8I_V3,
242+
SUNXI_FUNCTION(0x0, "gpio_in"),
243+
SUNXI_FUNCTION(0x1, "gpio_out"),
244+
SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
245+
SUNXI_FUNCTION(0x3, "lvds"), /* VN0 */
246+
SUNXI_FUNCTION(0x4, "emac")), /* TXCTL/TXEN */
247+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14),
248+
PINCTRL_SUN8I_V3,
249+
SUNXI_FUNCTION(0x0, "gpio_in"),
250+
SUNXI_FUNCTION(0x1, "gpio_out"),
251+
SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
252+
SUNXI_FUNCTION(0x3, "lvds"), /* VP1 */
253+
SUNXI_FUNCTION(0x4, "emac")), /* TXERR */
254+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15),
255+
PINCTRL_SUN8I_V3,
256+
SUNXI_FUNCTION(0x0, "gpio_in"),
257+
SUNXI_FUNCTION(0x1, "gpio_out"),
258+
SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
259+
SUNXI_FUNCTION(0x3, "lvds"), /* VN1 */
260+
SUNXI_FUNCTION(0x4, "emac")), /* CLKIN/COL */
261+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16),
262+
PINCTRL_SUN8I_V3,
263+
SUNXI_FUNCTION(0x0, "gpio_in"),
264+
SUNXI_FUNCTION(0x1, "gpio_out"),
265+
SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
266+
SUNXI_FUNCTION(0x3, "lvds"), /* VP2 */
267+
SUNXI_FUNCTION(0x4, "emac")), /* MDC */
268+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17),
269+
PINCTRL_SUN8I_V3,
270+
SUNXI_FUNCTION(0x0, "gpio_in"),
271+
SUNXI_FUNCTION(0x1, "gpio_out"),
272+
SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
273+
SUNXI_FUNCTION(0x3, "lvds"), /* VN2 */
274+
SUNXI_FUNCTION(0x4, "emac")), /* MDIO */
275+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 18),
276+
PINCTRL_SUN8I_V3,
277+
SUNXI_FUNCTION(0x0, "gpio_in"),
278+
SUNXI_FUNCTION(0x1, "gpio_out"),
279+
SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
280+
SUNXI_FUNCTION(0x3, "lvds")), /* VPC */
281+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 19),
282+
PINCTRL_SUN8I_V3,
283+
SUNXI_FUNCTION(0x0, "gpio_in"),
284+
SUNXI_FUNCTION(0x1, "gpio_out"),
285+
SUNXI_FUNCTION(0x2, "lcd"), /* DE */
286+
SUNXI_FUNCTION(0x3, "lvds")), /* VNC */
287+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 20),
288+
PINCTRL_SUN8I_V3,
289+
SUNXI_FUNCTION(0x0, "gpio_in"),
290+
SUNXI_FUNCTION(0x1, "gpio_out"),
291+
SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */
292+
SUNXI_FUNCTION(0x3, "lvds")), /* VP3 */
293+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 21),
294+
PINCTRL_SUN8I_V3,
295+
SUNXI_FUNCTION(0x0, "gpio_in"),
296+
SUNXI_FUNCTION(0x1, "gpio_out"),
297+
SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
298+
SUNXI_FUNCTION(0x3, "lvds")), /* VN3 */
101299
/* Hole */
102300
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
103301
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -291,6 +489,54 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
291489
SUNXI_FUNCTION(0x1, "gpio_out"),
292490
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
293491
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
492+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6),
493+
PINCTRL_SUN8I_V3,
494+
SUNXI_FUNCTION(0x0, "gpio_in"),
495+
SUNXI_FUNCTION(0x1, "gpio_out"),
496+
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
497+
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
498+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7),
499+
PINCTRL_SUN8I_V3,
500+
SUNXI_FUNCTION(0x0, "gpio_in"),
501+
SUNXI_FUNCTION(0x1, "gpio_out"),
502+
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
503+
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
504+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8),
505+
PINCTRL_SUN8I_V3,
506+
SUNXI_FUNCTION(0x0, "gpio_in"),
507+
SUNXI_FUNCTION(0x1, "gpio_out"),
508+
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
509+
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
510+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 9),
511+
PINCTRL_SUN8I_V3,
512+
SUNXI_FUNCTION(0x0, "gpio_in"),
513+
SUNXI_FUNCTION(0x1, "gpio_out"),
514+
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
515+
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
516+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 10),
517+
PINCTRL_SUN8I_V3,
518+
SUNXI_FUNCTION(0x0, "gpio_in"),
519+
SUNXI_FUNCTION(0x1, "gpio_out"),
520+
SUNXI_FUNCTION(0x2, "i2s"), /* SYNC */
521+
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
522+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 11),
523+
PINCTRL_SUN8I_V3,
524+
SUNXI_FUNCTION(0x0, "gpio_in"),
525+
SUNXI_FUNCTION(0x1, "gpio_out"),
526+
SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
527+
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
528+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 12),
529+
PINCTRL_SUN8I_V3,
530+
SUNXI_FUNCTION(0x0, "gpio_in"),
531+
SUNXI_FUNCTION(0x1, "gpio_out"),
532+
SUNXI_FUNCTION(0x2, "i2s"), /* DOUT */
533+
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
534+
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13),
535+
PINCTRL_SUN8I_V3,
536+
SUNXI_FUNCTION(0x0, "gpio_in"),
537+
SUNXI_FUNCTION(0x1, "gpio_out"),
538+
SUNXI_FUNCTION(0x2, "i2s"), /* DIN */
539+
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
294540
};
295541

296542
static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 };
@@ -305,13 +551,22 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
305551

306552
static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev)
307553
{
308-
return sunxi_pinctrl_init(pdev,
309-
&sun8i_v3s_pinctrl_data);
554+
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
555+
556+
return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3s_pinctrl_data,
557+
variant);
310558
}
311559

312560
static const struct of_device_id sun8i_v3s_pinctrl_match[] = {
313-
{ .compatible = "allwinner,sun8i-v3s-pinctrl", },
314-
{}
561+
{
562+
.compatible = "allwinner,sun8i-v3-pinctrl",
563+
.data = (void *)PINCTRL_SUN8I_V3
564+
},
565+
{
566+
.compatible = "allwinner,sun8i-v3s-pinctrl",
567+
.data = (void *)PINCTRL_SUN8I_V3S
568+
},
569+
{ },
315570
};
316571

317572
static struct platform_driver sun8i_v3s_pinctrl_driver = {

‎drivers/pinctrl/sunxi/pinctrl-sunxi.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,8 @@
9494
#define PINCTRL_SUN4I_A10 BIT(6)
9595
#define PINCTRL_SUN7I_A20 BIT(7)
9696
#define PINCTRL_SUN8I_R40 BIT(8)
97+
#define PINCTRL_SUN8I_V3 BIT(9)
98+
#define PINCTRL_SUN8I_V3S BIT(10)
9799

98100
#define PIO_POW_MOD_SEL_REG 0x340
99101

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