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Merge tag 'iommu-updates-v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel: "This update comes with: - Support for lockless operation in the ARM io-pgtable code. This is an important step to solve the scalability problems in the common dma-iommu code for ARM - Some Errata workarounds for ARM SMMU implemenations - Rewrite of the deferred IO/TLB flush code in the AMD IOMMU driver. The code suffered from very high flush rates, with the new implementation the flush rate is down to ~1% of what it was before - Support for amd_iommu=off when booting with kexec. The problem here was that the IOMMU driver bailed out early without disabling the iommu hardware, if it was enabled in the old kernel - The Rockchip IOMMU driver is now available on ARM64 - Align the return value of the iommu_ops->device_group call-backs to not miss error values - Preempt-disable optimizations in the Intel VT-d and common IOVA code to help Linux-RT - Various other small cleanups and fixes" * tag 'iommu-updates-v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (60 commits) iommu/vt-d: Constify intel_dma_ops iommu: Warn once when device_group callback returns NULL iommu/omap: Return ERR_PTR in device_group call-back iommu: Return ERR_PTR() values from device_group call-backs iommu/s390: Use iommu_group_get_for_dev() in s390_iommu_add_device() iommu/vt-d: Don't disable preemption while accessing deferred_flush() iommu/iova: Don't disable preempt around this_cpu_ptr() iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 iommu/arm-smmu-v3: Enable ACPI based HiSilicon CMD_PREFETCH quirk(erratum 161010701) iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model iommu/arm-smmu-v3, acpi: Add temporary Cavium SMMU-V3 IORT model number definitions iommu/io-pgtable-arm: Use dma_wmb() instead of wmb() when publishing table iommu/io-pgtable: depend on !GENERIC_ATOMIC64 when using COMPILE_TEST with LPAE iommu/arm-smmu-v3: Remove io-pgtable spinlock iommu/arm-smmu: Remove io-pgtable spinlock iommu/io-pgtable-arm-v7s: Support lockless operation iommu/io-pgtable-arm: Support lockless operation iommu/io-pgtable: Introduce explicit coherency iommu/io-pgtable-arm-v7s: Refactor split_blk_unmap ...
2 parents 6b1c776 + 6a70864 commit fb4e3be

22 files changed

+1233
-548
lines changed

‎Documentation/arm64/silicon-errata.txt

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,12 +61,15 @@ stable kernels.
6161
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
6262
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
6363
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
64-
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
6564
| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 |
65+
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
66+
| Cavium | ThunderX2 SMMUv3| #74 | N/A |
67+
| Cavium | ThunderX2 SMMUv3| #126 | N/A |
6668
| | | | |
6769
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
6870
| | | | |
6971
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
72+
| Hisilicon | Hip0{6,7} | #161010701 | N/A |
7073
| | | | |
7174
| Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
7275
| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |

‎Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,12 @@ the PCIe specification.
2626
* "priq" - PRI Queue not empty
2727
* "cmdq-sync" - CMD_SYNC complete
2828
* "gerror" - Global Error activated
29+
* "combined" - The combined interrupt is optional,
30+
and should only be provided if the
31+
hardware supports just a single,
32+
combined interrupt line.
33+
If provided, then the combined interrupt
34+
will be used in preference to any others.
2935

3036
- #iommu-cells : See the generic IOMMU binding described in
3137
devicetree/bindings/pci/pci-iommu.txt
@@ -49,6 +55,12 @@ the PCIe specification.
4955
- hisilicon,broken-prefetch-cmd
5056
: Avoid sending CMD_PREFETCH_* commands to the SMMU.
5157

58+
- cavium,cn9900-broken-page1-regspace
59+
: Replaces all page 1 offsets used for EVTQ_PROD/CONS,
60+
PRIQ_PROD/CONS register access with page 0 offsets.
61+
Set for Cavium ThunderX2 silicon that doesn't support
62+
SMMU page1 register space.
63+
5264
** Example
5365

5466
smmu@2b400000 {

‎drivers/acpi/arm64/iort.c

Lines changed: 63 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,11 @@
3131
#define IORT_IOMMU_TYPE ((1 << ACPI_IORT_NODE_SMMU) | \
3232
(1 << ACPI_IORT_NODE_SMMU_V3))
3333

34+
/* Until ACPICA headers cover IORT rev. C */
35+
#ifndef ACPI_IORT_SMMU_V3_CAVIUM_CN99XX
36+
#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x2
37+
#endif
38+
3439
struct iort_its_msi_chip {
3540
struct list_head list;
3641
struct fwnode_handle *fw_node;
@@ -819,6 +824,36 @@ static int __init arm_smmu_v3_count_resources(struct acpi_iort_node *node)
819824
return num_res;
820825
}
821826

827+
static bool arm_smmu_v3_is_combined_irq(struct acpi_iort_smmu_v3 *smmu)
828+
{
829+
/*
830+
* Cavium ThunderX2 implementation doesn't not support unique
831+
* irq line. Use single irq line for all the SMMUv3 interrupts.
832+
*/
833+
if (smmu->model != ACPI_IORT_SMMU_V3_CAVIUM_CN99XX)
834+
return false;
835+
836+
/*
837+
* ThunderX2 doesn't support MSIs from the SMMU, so we're checking
838+
* SPI numbers here.
839+
*/
840+
return smmu->event_gsiv == smmu->pri_gsiv &&
841+
smmu->event_gsiv == smmu->gerr_gsiv &&
842+
smmu->event_gsiv == smmu->sync_gsiv;
843+
}
844+
845+
static unsigned long arm_smmu_v3_resource_size(struct acpi_iort_smmu_v3 *smmu)
846+
{
847+
/*
848+
* Override the size, for Cavium ThunderX2 implementation
849+
* which doesn't support the page 1 SMMU register space.
850+
*/
851+
if (smmu->model == ACPI_IORT_SMMU_V3_CAVIUM_CN99XX)
852+
return SZ_64K;
853+
854+
return SZ_128K;
855+
}
856+
822857
static void __init arm_smmu_v3_init_resources(struct resource *res,
823858
struct acpi_iort_node *node)
824859
{
@@ -829,30 +864,38 @@ static void __init arm_smmu_v3_init_resources(struct resource *res,
829864
smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
830865

831866
res[num_res].start = smmu->base_address;
832-
res[num_res].end = smmu->base_address + SZ_128K - 1;
867+
res[num_res].end = smmu->base_address +
868+
arm_smmu_v3_resource_size(smmu) - 1;
833869
res[num_res].flags = IORESOURCE_MEM;
834870

835871
num_res++;
872+
if (arm_smmu_v3_is_combined_irq(smmu)) {
873+
if (smmu->event_gsiv)
874+
acpi_iort_register_irq(smmu->event_gsiv, "combined",
875+
ACPI_EDGE_SENSITIVE,
876+
&res[num_res++]);
877+
} else {
836878

837-
if (smmu->event_gsiv)
838-
acpi_iort_register_irq(smmu->event_gsiv, "eventq",
839-
ACPI_EDGE_SENSITIVE,
840-
&res[num_res++]);
841-
842-
if (smmu->pri_gsiv)
843-
acpi_iort_register_irq(smmu->pri_gsiv, "priq",
844-
ACPI_EDGE_SENSITIVE,
845-
&res[num_res++]);
846-
847-
if (smmu->gerr_gsiv)
848-
acpi_iort_register_irq(smmu->gerr_gsiv, "gerror",
849-
ACPI_EDGE_SENSITIVE,
850-
&res[num_res++]);
851-
852-
if (smmu->sync_gsiv)
853-
acpi_iort_register_irq(smmu->sync_gsiv, "cmdq-sync",
854-
ACPI_EDGE_SENSITIVE,
855-
&res[num_res++]);
879+
if (smmu->event_gsiv)
880+
acpi_iort_register_irq(smmu->event_gsiv, "eventq",
881+
ACPI_EDGE_SENSITIVE,
882+
&res[num_res++]);
883+
884+
if (smmu->pri_gsiv)
885+
acpi_iort_register_irq(smmu->pri_gsiv, "priq",
886+
ACPI_EDGE_SENSITIVE,
887+
&res[num_res++]);
888+
889+
if (smmu->gerr_gsiv)
890+
acpi_iort_register_irq(smmu->gerr_gsiv, "gerror",
891+
ACPI_EDGE_SENSITIVE,
892+
&res[num_res++]);
893+
894+
if (smmu->sync_gsiv)
895+
acpi_iort_register_irq(smmu->sync_gsiv, "cmdq-sync",
896+
ACPI_EDGE_SENSITIVE,
897+
&res[num_res++]);
898+
}
856899
}
857900

858901
static bool __init arm_smmu_v3_is_coherent(struct acpi_iort_node *node)

‎drivers/iommu/Kconfig

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ config IOMMU_IO_PGTABLE
2323
config IOMMU_IO_PGTABLE_LPAE
2424
bool "ARMv7/v8 Long Descriptor Format"
2525
select IOMMU_IO_PGTABLE
26-
depends on HAS_DMA && (ARM || ARM64 || COMPILE_TEST)
26+
depends on HAS_DMA && (ARM || ARM64 || (COMPILE_TEST && !GENERIC_ATOMIC64))
2727
help
2828
Enable support for the ARM long descriptor pagetable format.
2929
This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page
@@ -219,7 +219,7 @@ config OMAP_IOMMU_DEBUG
219219

220220
config ROCKCHIP_IOMMU
221221
bool "Rockchip IOMMU Support"
222-
depends on ARM
222+
depends on ARM || ARM64
223223
depends on ARCH_ROCKCHIP || COMPILE_TEST
224224
select IOMMU_API
225225
select ARM_DMA_USE_IOMMU
@@ -274,7 +274,7 @@ config EXYNOS_IOMMU_DEBUG
274274

275275
config IPMMU_VMSA
276276
bool "Renesas VMSA-compatible IPMMU"
277-
depends on ARM_LPAE
277+
depends on ARM || IOMMU_DMA
278278
depends on ARCH_RENESAS || COMPILE_TEST
279279
select IOMMU_API
280280
select IOMMU_IO_PGTABLE_LPAE

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