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| 1 | +* Mediatek UART APDMA Controller |
| 2 | + |
| 3 | +Required properties: |
| 4 | +- compatible should contain: |
| 5 | + * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA |
| 6 | + * "mediatek,mt6577-uart-dma" for MT6577 and all of the above |
| 7 | + |
| 8 | +- reg: The base address of the APDMA register bank. |
| 9 | + |
| 10 | +- interrupts: A single interrupt specifier. |
| 11 | + One interrupt per dma-requests, or 8 if no dma-requests property is present |
| 12 | + |
| 13 | +- dma-requests: The number of DMA channels |
| 14 | + |
| 15 | +- clocks : Must contain an entry for each entry in clock-names. |
| 16 | + See ../clocks/clock-bindings.txt for details. |
| 17 | +- clock-names: The APDMA clock for register accesses |
| 18 | + |
| 19 | +- mediatek,dma-33bits: Present if the DMA requires support |
| 20 | + |
| 21 | +Examples: |
| 22 | + |
| 23 | + apdma: dma-controller@11000400 { |
| 24 | + compatible = "mediatek,mt2712-uart-dma"; |
| 25 | + reg = <0 0x11000400 0 0x80>, |
| 26 | + <0 0x11000480 0 0x80>, |
| 27 | + <0 0x11000500 0 0x80>, |
| 28 | + <0 0x11000580 0 0x80>, |
| 29 | + <0 0x11000600 0 0x80>, |
| 30 | + <0 0x11000680 0 0x80>, |
| 31 | + <0 0x11000700 0 0x80>, |
| 32 | + <0 0x11000780 0 0x80>, |
| 33 | + <0 0x11000800 0 0x80>, |
| 34 | + <0 0x11000880 0 0x80>, |
| 35 | + <0 0x11000900 0 0x80>, |
| 36 | + <0 0x11000980 0 0x80>; |
| 37 | + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, |
| 38 | + <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, |
| 39 | + <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, |
| 40 | + <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, |
| 41 | + <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, |
| 42 | + <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, |
| 43 | + <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, |
| 44 | + <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>, |
| 45 | + <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>, |
| 46 | + <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>, |
| 47 | + <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>, |
| 48 | + <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>; |
| 49 | + dma-requests = <12>; |
| 50 | + clocks = <&pericfg CLK_PERI_AP_DMA>; |
| 51 | + clock-names = "apdma"; |
| 52 | + mediatek,dma-33bits; |
| 53 | + #dma-cells = <1>; |
| 54 | + }; |
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