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vadimp-nvidiajwrdegoede
vadimp-nvidia
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jwrdegoede
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platform: mellanox: Introduce support for next-generation 800GB/s switch
Introduce support for Nvidia next-generation 800GB/s ethernet switch SN5600. SN5600 is 51.2 Tbps Ethernet switch based on Nvidia Spectrum-4 ASIC. It can provide up to 64x800Gb/s (ETH) full bidirectional bandwidth per port using PAM-4 modulations. The system supports 64 Belly to Belly 2x4 OSFP cages. The switch was designed to fit standard 2U racks. Features: - 64 OSFP ports support 800GbE - 10GbE speed. - Additional 25GbE - 1GbE service port on the front panel. - Air-cooled with 3 + 1 redundant fan units. - 1 + 1 redundant 3000W or 3600W PSUs. - System management board is based on Intel Coffee-lake CPU E-2276 with secure-boot support. Signed-off-by: Vadim Pasternak <[email protected]> Reviewed-by: Michael Shych <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hans de Goede <[email protected]>
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‎drivers/platform/x86/mlx-platform.c

Lines changed: 180 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -253,6 +253,7 @@
253253
#define MLXPLAT_CPLD_CH3_ETH_MODULAR 43
254254
#define MLXPLAT_CPLD_CH4_ETH_MODULAR 51
255255
#define MLXPLAT_CPLD_CH2_RACK_SWITCH 18
256+
#define MLXPLAT_CPLD_CH2_NG800 34
256257

257258
/* Number of LPC attached MUX platform devices */
258259
#define MLXPLAT_CPLD_LPC_MUX_DEVS 4
@@ -503,6 +504,37 @@ static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = {
503504

504505
};
505506

507+
/* Platform channels for ng800 system family */
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static const int mlxplat_ng800_channels[] = {
509+
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
510+
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32
511+
};
512+
513+
/* Platform ng800 mux data */
514+
static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = {
515+
{
516+
.parent = 1,
517+
.base_nr = MLXPLAT_CPLD_CH1,
518+
.write_only = 1,
519+
.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
520+
.reg_size = 1,
521+
.idle_in_use = 1,
522+
.values = mlxplat_ng800_channels,
523+
.n_values = ARRAY_SIZE(mlxplat_ng800_channels),
524+
},
525+
{
526+
.parent = 1,
527+
.base_nr = MLXPLAT_CPLD_CH2_NG800,
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.write_only = 1,
529+
.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
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.reg_size = 1,
531+
.idle_in_use = 1,
532+
.values = mlxplat_msn21xx_channels,
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.n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
534+
},
535+
536+
};
537+
506538
/* Platform hotplug devices */
507539
static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
508540
{
@@ -522,6 +554,15 @@ static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = {
522554
},
523555
};
524556

557+
static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = {
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{
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I2C_BOARD_INFO("dps460", 0x59),
560+
},
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{
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I2C_BOARD_INFO("dps460", 0x5a),
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},
564+
};
565+
525566
static struct i2c_board_info mlxplat_mlxcpld_fan[] = {
526567
{
527568
I2C_BOARD_INFO("24c32", 0x50),
@@ -601,6 +642,23 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = {
601642
},
602643
};
603644

645+
static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = {
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{
647+
.label = "pwr1",
648+
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(0),
650+
.hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[0],
651+
.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
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},
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{
654+
.label = "pwr2",
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = BIT(1),
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.hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1],
658+
.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
659+
},
660+
};
661+
604662
static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {
605663
{
606664
.label = "fan1",
@@ -1224,6 +1282,47 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
12241282
}
12251283
};
12261284

1285+
static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = {
1286+
{
1287+
.data = mlxplat_mlxcpld_default_ng_psu_items_data,
1288+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1289+
.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1290+
.mask = MLXPLAT_CPLD_PSU_EXT_MASK,
1291+
.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1292+
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data),
1293+
.inversed = 1,
1294+
.health = false,
1295+
},
1296+
{
1297+
.data = mlxplat_mlxcpld_default_pwr_ng800_items_data,
1298+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1299+
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1300+
.mask = MLXPLAT_CPLD_PWR_EXT_MASK,
1301+
.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1302+
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_ng800_items_data),
1303+
.inversed = 0,
1304+
.health = false,
1305+
},
1306+
{
1307+
.data = mlxplat_mlxcpld_default_ng_fan_items_data,
1308+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1309+
.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1310+
.mask = MLXPLAT_CPLD_FAN_NG_MASK,
1311+
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
1312+
.inversed = 1,
1313+
.health = false,
1314+
},
1315+
{
1316+
.data = mlxplat_mlxcpld_default_asic_items_data,
1317+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1318+
.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1319+
.mask = MLXPLAT_CPLD_ASIC_MASK,
1320+
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
1321+
.inversed = 0,
1322+
.health = true,
1323+
},
1324+
};
1325+
12271326
static
12281327
struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
12291328
.items = mlxplat_mlxcpld_ext_items,
@@ -1234,6 +1333,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
12341333
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
12351334
};
12361335

1336+
static
1337+
struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = {
1338+
.items = mlxplat_mlxcpld_ng800_items,
1339+
.counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items),
1340+
.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1341+
.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
1342+
.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1343+
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
1344+
};
1345+
12371346
static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = {
12381347
{
12391348
.label = "pwr1",
@@ -3093,6 +3202,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
30933202
.mask = GENMASK(7, 0) & ~BIT(7),
30943203
.mode = 0644,
30953204
},
3205+
{
3206+
.label = "clk_brd_prog_en",
3207+
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3208+
.mask = GENMASK(7, 0) & ~BIT(1),
3209+
.mode = 0644,
3210+
.secured = 1,
3211+
},
30963212
{
30973213
.label = "erot1_recovery",
30983214
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
@@ -3221,6 +3337,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
32213337
.mask = GENMASK(7, 0) & ~BIT(6),
32223338
.mode = 0444,
32233339
},
3340+
{
3341+
.label = "reset_ac_ok_fail",
3342+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3343+
.mask = GENMASK(7, 0) & ~BIT(7),
3344+
.mode = 0444,
3345+
},
32243346
{
32253347
.label = "psu1_on",
32263348
.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
@@ -3302,6 +3424,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
33023424
.bit = 5,
33033425
.mode = 0444,
33043426
},
3427+
{
3428+
.label = "pwr_converter_prog_en",
3429+
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3430+
.mask = GENMASK(7, 0) & ~BIT(0),
3431+
.mode = 0644,
3432+
.secured = 1,
3433+
},
33053434
{
33063435
.label = "vpd_wp",
33073436
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
@@ -3326,6 +3455,30 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
33263455
.mask = GENMASK(7, 0) & ~BIT(1),
33273456
.mode = 0444,
33283457
},
3458+
{
3459+
.label = "clk_brd1_boot_fail",
3460+
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3461+
.mask = GENMASK(7, 0) & ~BIT(4),
3462+
.mode = 0444,
3463+
},
3464+
{
3465+
.label = "clk_brd2_boot_fail",
3466+
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3467+
.mask = GENMASK(7, 0) & ~BIT(5),
3468+
.mode = 0444,
3469+
},
3470+
{
3471+
.label = "clk_brd_fail",
3472+
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3473+
.mask = GENMASK(7, 0) & ~BIT(6),
3474+
.mode = 0444,
3475+
},
3476+
{
3477+
.label = "asic_pg_fail",
3478+
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3479+
.mask = GENMASK(7, 0) & ~BIT(7),
3480+
.mode = 0444,
3481+
},
33293482
{
33303483
.label = "spi_chnl_select",
33313484
.reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT,
@@ -5211,6 +5364,27 @@ static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dm
52115364
return 1;
52125365
}
52135366

5367+
static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi)
5368+
{
5369+
int i;
5370+
5371+
mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5372+
mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data);
5373+
mlxplat_mux_data = mlxplat_ng800_mux_data;
5374+
mlxplat_hotplug = &mlxplat_mlxcpld_ng800_data;
5375+
mlxplat_hotplug->deferred_nr =
5376+
mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5377+
mlxplat_led = &mlxplat_default_ng_led_data;
5378+
mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
5379+
mlxplat_fan = &mlxplat_default_fan_data;
5380+
for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5381+
mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5382+
mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5383+
mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
5384+
5385+
return 1;
5386+
}
5387+
52145388
static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
52155389
{
52165390
.callback = mlxplat_dmi_default_wc_matched,
@@ -5287,6 +5461,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
52875461
DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"),
52885462
},
52895463
},
5464+
{
5465+
.callback = mlxplat_dmi_ng800_matched,
5466+
.matches = {
5467+
DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"),
5468+
},
5469+
},
52905470
{
52915471
.callback = mlxplat_dmi_chassis_blade_matched,
52925472
.matches = {

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