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torvaldstorvalds
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Merge tag 'drm-for-v4.16-part2-fixes' of git://people.freedesktop.org/~airlied/linux
Pull more drm updates from Dave Airlie: "Ben missed sending his nouveau tree, but he really didn't have much stuff in it: - GP108 acceleration support is enabled by "secure boot" support - some clockgating work on Kepler, and bunch of fixes - the bulk of the diff is regenerated firmware files, the change to them really isn't that large. Otherwise this contains regular Intel and AMDGPU fixes" * tag 'drm-for-v4.16-part2-fixes' of git://people.freedesktop.org/~airlied/linux: (59 commits) drm/i915/bios: add DP max link rate to VBT child device struct drm/i915/cnp: Properly handle VBT ddc pin out of bounds. drm/i915/cnp: Ignore VBT request for know invalid DDC pin. drm/i915/cmdparser: Do not check past the cmd length. drm/i915/cmdparser: Check reg_table_count before derefencing. drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing drm/i915/gvt: Use KVM r/w to access guest opregion drm/i915/gvt: Fix aperture read/write emulation when enable x-no-mmap=on drm/i915/gvt: only reset execlist state of one engine during VM engine reset drm/i915/gvt: refine intel_vgpu_submission_ops as per engine ops drm/amdgpu: re-enable CGCG on CZ and disable on ST drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning drm/nouveau/mmu: Fix trailing semicolon drm/nouveau: Introduce NvPmEnableGating option drm/nouveau: Add support for SLCG for Kepler2 drm/nouveau: Add support for BLCG on Kepler2 drm/nouveau: Add support for BLCG on Kepler1 drm/nouveau: Add support for basic clockgating on Kepler1 drm/nouveau/kms/nv50: fix handling of gamma since atomic conversion drm/nouveau/kms/nv50: use INTERPOLATE_257_UNITY_RANGE LUT on newer chipsets ...
2 parents 9e95dae + 94fc27a commit fe26adf

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90 files changed

+3168
-1788
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -179,8 +179,12 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
179179

180180
amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
181181

182-
/* Using pipes 2/3 from MEC 2 seems cause problems */
183-
if (mec == 1 && pipe > 1)
182+
/*
183+
* 1. Using pipes 2/3 from MEC 2 seems cause problems.
184+
* 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
185+
* only can be issued on queue 0.
186+
*/
187+
if ((mec == 1 && pipe > 1) || queue != 0)
184188
continue;
185189

186190
ring->me = mec + 1;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2262,12 +2262,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
22622262
{
22632263
const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
22642264
AMDGPU_VM_PTE_COUNT(adev) * 8);
2265+
uint64_t init_pde_value = 0, flags;
22652266
unsigned ring_instance;
22662267
struct amdgpu_ring *ring;
22672268
struct drm_sched_rq *rq;
2269+
unsigned long size;
22682270
int r, i;
2269-
u64 flags;
2270-
uint64_t init_pde_value = 0;
22712271

22722272
vm->va = RB_ROOT_CACHED;
22732273
for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
@@ -2318,29 +2318,21 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
23182318
flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
23192319
AMDGPU_GEM_CREATE_SHADOW);
23202320

2321-
r = amdgpu_bo_create(adev,
2322-
amdgpu_vm_bo_size(adev, adev->vm_manager.root_level),
2323-
align, true,
2324-
AMDGPU_GEM_DOMAIN_VRAM,
2325-
flags,
2326-
NULL, NULL, init_pde_value, &vm->root.base.bo);
2321+
size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
2322+
r = amdgpu_bo_create(adev, size, align, true, AMDGPU_GEM_DOMAIN_VRAM,
2323+
flags, NULL, NULL, init_pde_value,
2324+
&vm->root.base.bo);
23272325
if (r)
23282326
goto error_free_sched_entity;
23292327

2328+
r = amdgpu_bo_reserve(vm->root.base.bo, true);
2329+
if (r)
2330+
goto error_free_root;
2331+
23302332
vm->root.base.vm = vm;
23312333
list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);
2332-
INIT_LIST_HEAD(&vm->root.base.vm_status);
2333-
2334-
if (vm->use_cpu_for_update) {
2335-
r = amdgpu_bo_reserve(vm->root.base.bo, false);
2336-
if (r)
2337-
goto error_free_root;
2338-
2339-
r = amdgpu_bo_kmap(vm->root.base.bo, NULL);
2340-
amdgpu_bo_unreserve(vm->root.base.bo);
2341-
if (r)
2342-
goto error_free_root;
2343-
}
2334+
list_add_tail(&vm->root.base.vm_status, &vm->evicted);
2335+
amdgpu_bo_unreserve(vm->root.base.bo);
23442336

23452337
if (pasid) {
23462338
unsigned long flags;

‎drivers/gpu/drm/amd/amdgpu/vega10_ih.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -278,19 +278,21 @@ static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev)
278278
/* Track retry faults in per-VM fault FIFO. */
279279
spin_lock(&adev->vm_manager.pasid_lock);
280280
vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
281-
spin_unlock(&adev->vm_manager.pasid_lock);
282-
if (WARN_ON_ONCE(!vm)) {
281+
if (!vm) {
283282
/* VM not found, process it normally */
283+
spin_unlock(&adev->vm_manager.pasid_lock);
284284
amdgpu_ih_clear_fault(adev, key);
285285
return true;
286286
}
287287
/* No locking required with single writer and single reader */
288288
r = kfifo_put(&vm->faults, key);
289289
if (!r) {
290290
/* FIFO is full. Ignore it until there is space */
291+
spin_unlock(&adev->vm_manager.pasid_lock);
291292
amdgpu_ih_clear_fault(adev, key);
292293
goto ignore_iv;
293294
}
295+
spin_unlock(&adev->vm_manager.pasid_lock);
294296

295297
/* It's the first fault for this address, process it normally */
296298
return true;

‎drivers/gpu/drm/amd/amdgpu/vi.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1049,7 +1049,6 @@ static int vi_common_early_init(void *handle)
10491049
AMD_CG_SUPPORT_GFX_CP_LS |
10501050
AMD_CG_SUPPORT_GFX_CGTS |
10511051
AMD_CG_SUPPORT_GFX_CGTS_LS |
1052-
AMD_CG_SUPPORT_GFX_CGCG |
10531052
AMD_CG_SUPPORT_GFX_CGLS |
10541053
AMD_CG_SUPPORT_BIF_LS |
10551054
AMD_CG_SUPPORT_HDP_MGCG |

‎drivers/gpu/drm/i915/gvt/cfg_space.c

Lines changed: 1 addition & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -119,16 +119,6 @@ static int map_aperture(struct intel_vgpu *vgpu, bool map)
119119
if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
120120
return 0;
121121

122-
if (map) {
123-
vgpu->gm.aperture_va = memremap(aperture_pa, aperture_sz,
124-
MEMREMAP_WC);
125-
if (!vgpu->gm.aperture_va)
126-
return -ENOMEM;
127-
} else {
128-
memunmap(vgpu->gm.aperture_va);
129-
vgpu->gm.aperture_va = NULL;
130-
}
131-
132122
val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];
133123
if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
134124
val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
@@ -141,11 +131,8 @@ static int map_aperture(struct intel_vgpu *vgpu, bool map)
141131
aperture_pa >> PAGE_SHIFT,
142132
aperture_sz >> PAGE_SHIFT,
143133
map);
144-
if (ret) {
145-
memunmap(vgpu->gm.aperture_va);
146-
vgpu->gm.aperture_va = NULL;
134+
if (ret)
147135
return ret;
148-
}
149136

150137
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
151138
return 0;

‎drivers/gpu/drm/i915/gvt/dmabuf.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -472,7 +472,6 @@ int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id)
472472
ret = PTR_ERR(dmabuf);
473473
goto out_free_gem;
474474
}
475-
obj->base.dma_buf = dmabuf;
476475

477476
i915_gem_object_put(obj);
478477

‎drivers/gpu/drm/i915/gvt/execlist.c

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -521,24 +521,23 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu, int ring_id)
521521

522522
ctx_status_ptr_reg = execlist_ring_mmio(vgpu->gvt, ring_id,
523523
_EL_OFFSET_STATUS_PTR);
524-
525524
ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);
526525
ctx_status_ptr.read_ptr = 0;
527526
ctx_status_ptr.write_ptr = 0x7;
528527
vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
529528
}
530529

531-
static void clean_execlist(struct intel_vgpu *vgpu)
530+
static void clean_execlist(struct intel_vgpu *vgpu, unsigned long engine_mask)
532531
{
533-
enum intel_engine_id i;
532+
unsigned int tmp;
533+
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
534534
struct intel_engine_cs *engine;
535+
struct intel_vgpu_submission *s = &vgpu->submission;
535536

536-
for_each_engine(engine, vgpu->gvt->dev_priv, i) {
537-
struct intel_vgpu_submission *s = &vgpu->submission;
538-
539-
kfree(s->ring_scan_buffer[i]);
540-
s->ring_scan_buffer[i] = NULL;
541-
s->ring_scan_buffer_size[i] = 0;
537+
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
538+
kfree(s->ring_scan_buffer[engine->id]);
539+
s->ring_scan_buffer[engine->id] = NULL;
540+
s->ring_scan_buffer_size[engine->id] = 0;
542541
}
543542
}
544543

@@ -553,9 +552,10 @@ static void reset_execlist(struct intel_vgpu *vgpu,
553552
init_vgpu_execlist(vgpu, engine->id);
554553
}
555554

556-
static int init_execlist(struct intel_vgpu *vgpu)
555+
static int init_execlist(struct intel_vgpu *vgpu,
556+
unsigned long engine_mask)
557557
{
558-
reset_execlist(vgpu, ALL_ENGINES);
558+
reset_execlist(vgpu, engine_mask);
559559
return 0;
560560
}
561561

‎drivers/gpu/drm/i915/gvt/gtt.c

Lines changed: 19 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -997,19 +997,22 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
997997
static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt)
998998
{
999999
struct intel_vgpu *vgpu = spt->vgpu;
1000+
struct intel_gvt *gvt = vgpu->gvt;
1001+
struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
10001002
struct intel_vgpu_ppgtt_spt *s;
10011003
struct intel_gvt_gtt_entry se, ge;
1002-
unsigned long i;
1004+
unsigned long gfn, i;
10031005
int ret;
10041006

10051007
trace_spt_change(spt->vgpu->id, "born", spt,
10061008
spt->guest_page.track.gfn, spt->shadow_page.type);
10071009

10081010
if (gtt_type_is_pte_pt(spt->shadow_page.type)) {
10091011
for_each_present_guest_entry(spt, &ge, i) {
1010-
ret = gtt_entry_p2m(vgpu, &ge, &se);
1011-
if (ret)
1012-
goto fail;
1012+
gfn = ops->get_pfn(&ge);
1013+
if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn) ||
1014+
gtt_entry_p2m(vgpu, &ge, &se))
1015+
ops->set_pfn(&se, gvt->gtt.scratch_mfn);
10131016
ppgtt_set_shadow_entry(spt, &se, i);
10141017
}
10151018
return 0;
@@ -1906,7 +1909,7 @@ static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
19061909
struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
19071910
struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
19081911
unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
1909-
unsigned long gma;
1912+
unsigned long gma, gfn;
19101913
struct intel_gvt_gtt_entry e, m;
19111914
int ret;
19121915

@@ -1925,6 +1928,16 @@ static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
19251928
bytes);
19261929

19271930
if (ops->test_present(&e)) {
1931+
gfn = ops->get_pfn(&e);
1932+
1933+
/* one PTE update may be issued in multiple writes and the
1934+
* first write may not construct a valid gfn
1935+
*/
1936+
if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
1937+
ops->set_pfn(&m, gvt->gtt.scratch_mfn);
1938+
goto out;
1939+
}
1940+
19281941
ret = gtt_entry_p2m(vgpu, &e, &m);
19291942
if (ret) {
19301943
gvt_vgpu_err("fail to translate guest gtt entry\n");
@@ -1939,6 +1952,7 @@ static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
19391952
ops->set_pfn(&m, gvt->gtt.scratch_mfn);
19401953
}
19411954

1955+
out:
19421956
ggtt_set_shadow_entry(ggtt_mm, &m, g_gtt_index);
19431957
gtt_invalidate(gvt->dev_priv);
19441958
ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);

‎drivers/gpu/drm/i915/gvt/gvt.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,6 @@ struct intel_gvt_device_info {
8282
struct intel_vgpu_gm {
8383
u64 aperture_sz;
8484
u64 hidden_sz;
85-
void *aperture_va;
8685
struct drm_mm_node low_gm_node;
8786
struct drm_mm_node high_gm_node;
8887
};
@@ -127,7 +126,6 @@ struct intel_vgpu_irq {
127126
struct intel_vgpu_opregion {
128127
bool mapped;
129128
void *va;
130-
void *va_gopregion;
131129
u32 gfn[INTEL_GVT_OPREGION_PAGES];
132130
};
133131

@@ -152,8 +150,8 @@ enum {
152150

153151
struct intel_vgpu_submission_ops {
154152
const char *name;
155-
int (*init)(struct intel_vgpu *vgpu);
156-
void (*clean)(struct intel_vgpu *vgpu);
153+
int (*init)(struct intel_vgpu *vgpu, unsigned long engine_mask);
154+
void (*clean)(struct intel_vgpu *vgpu, unsigned long engine_mask);
157155
void (*reset)(struct intel_vgpu *vgpu, unsigned long engine_mask);
158156
};
159157

‎drivers/gpu/drm/i915/gvt/handlers.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1494,7 +1494,6 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
14941494
static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
14951495
void *p_data, unsigned int bytes)
14961496
{
1497-
struct intel_vgpu_submission *s = &vgpu->submission;
14981497
u32 data = *(u32 *)p_data;
14991498
int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
15001499
bool enable_execlist;
@@ -1523,11 +1522,9 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
15231522
if (!enable_execlist)
15241523
return 0;
15251524

1526-
if (s->active)
1527-
return 0;
1528-
15291525
ret = intel_vgpu_select_submission_ops(vgpu,
1530-
INTEL_VGPU_EXECLIST_SUBMISSION);
1526+
ENGINE_MASK(ring_id),
1527+
INTEL_VGPU_EXECLIST_SUBMISSION);
15311528
if (ret)
15321529
return ret;
15331530

@@ -2843,6 +2840,9 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
28432840
MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
28442841
MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
28452842
MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
2843+
MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
2844+
MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
2845+
MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
28462846
MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
28472847
MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
28482848
MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);

‎drivers/gpu/drm/i915/gvt/hypercall.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,7 @@ struct intel_gvt_mpt {
5858
int (*set_opregion)(void *vgpu);
5959
int (*get_vfio_device)(void *vgpu);
6060
void (*put_vfio_device)(void *vgpu);
61+
bool (*is_valid_gfn)(unsigned long handle, unsigned long gfn);
6162
};
6263

6364
extern struct intel_gvt_mpt xengt_mpt;

‎drivers/gpu/drm/i915/gvt/kvmgt.c

Lines changed: 50 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -651,6 +651,39 @@ static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off,
651651
return ret;
652652
}
653653

654+
static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, uint64_t off)
655+
{
656+
return off >= vgpu_aperture_offset(vgpu) &&
657+
off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu);
658+
}
659+
660+
static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t off,
661+
void *buf, unsigned long count, bool is_write)
662+
{
663+
void *aperture_va;
664+
665+
if (!intel_vgpu_in_aperture(vgpu, off) ||
666+
!intel_vgpu_in_aperture(vgpu, off + count)) {
667+
gvt_vgpu_err("Invalid aperture offset %llu\n", off);
668+
return -EINVAL;
669+
}
670+
671+
aperture_va = io_mapping_map_wc(&vgpu->gvt->dev_priv->ggtt.iomap,
672+
ALIGN_DOWN(off, PAGE_SIZE),
673+
count + offset_in_page(off));
674+
if (!aperture_va)
675+
return -EIO;
676+
677+
if (is_write)
678+
memcpy(aperture_va + offset_in_page(off), buf, count);
679+
else
680+
memcpy(buf, aperture_va + offset_in_page(off), count);
681+
682+
io_mapping_unmap(aperture_va);
683+
684+
return 0;
685+
}
686+
654687
static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
655688
size_t count, loff_t *ppos, bool is_write)
656689
{
@@ -679,8 +712,7 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
679712
buf, count, is_write);
680713
break;
681714
case VFIO_PCI_BAR2_REGION_INDEX:
682-
ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_2, pos,
683-
buf, count, is_write);
715+
ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write);
684716
break;
685717
case VFIO_PCI_BAR1_REGION_INDEX:
686718
case VFIO_PCI_BAR3_REGION_INDEX:
@@ -1575,6 +1607,21 @@ static unsigned long kvmgt_virt_to_pfn(void *addr)
15751607
return PFN_DOWN(__pa(addr));
15761608
}
15771609

1610+
static bool kvmgt_is_valid_gfn(unsigned long handle, unsigned long gfn)
1611+
{
1612+
struct kvmgt_guest_info *info;
1613+
struct kvm *kvm;
1614+
1615+
if (!handle_valid(handle))
1616+
return false;
1617+
1618+
info = (struct kvmgt_guest_info *)handle;
1619+
kvm = info->kvm;
1620+
1621+
return kvm_is_visible_gfn(kvm, gfn);
1622+
1623+
}
1624+
15781625
struct intel_gvt_mpt kvmgt_mpt = {
15791626
.host_init = kvmgt_host_init,
15801627
.host_exit = kvmgt_host_exit,
@@ -1590,6 +1637,7 @@ struct intel_gvt_mpt kvmgt_mpt = {
15901637
.set_opregion = kvmgt_set_opregion,
15911638
.get_vfio_device = kvmgt_get_vfio_device,
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.put_vfio_device = kvmgt_put_vfio_device,
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.is_valid_gfn = kvmgt_is_valid_gfn,
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};
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EXPORT_SYMBOL_GPL(kvmgt_mpt);
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