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Sathya Perladavem330
Sathya Perla
authored and
davem330
committed
be2net: adding support for Lancer family of CNAs
Key changes are: - EQ ids are not assigned consecutively in Lancer. So, fix mapping of MSIx vector to EQ-id. - BAR mapping and some req locations different for Lancer. - TCP,UDP,IP checksum fields must be compulsorily set in TX wrb for TSO in Lancer. - CEV_IST reg not present in Lancer; so, peek into event queue to check for new entries - cq_create and mcc_create cmd interface is different for Lancer; handle accordingly Signed-off-by: Padmanabh Ratnakar <[email protected]> Signed-off-by: Sathya Perla <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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5 files changed

+301
-92
lines changed

5 files changed

+301
-92
lines changed

‎drivers/net/benet/be.h

Lines changed: 26 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -38,22 +38,27 @@
3838
#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
3939
#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
4040
#define OC_NAME "Emulex OneConnect 10Gbps NIC"
41-
#define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)"
41+
#define OC_NAME_BE OC_NAME "(be3)"
42+
#define OC_NAME_LANCER OC_NAME "(Lancer)"
4243
#define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
4344

4445
#define BE_VENDOR_ID 0x19a2
46+
#define EMULEX_VENDOR_ID 0x10df
4547
#define BE_DEVICE_ID1 0x211
4648
#define BE_DEVICE_ID2 0x221
47-
#define OC_DEVICE_ID1 0x700
48-
#define OC_DEVICE_ID2 0x710
49+
#define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
50+
#define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
51+
#define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
4952

5053
static inline char *nic_name(struct pci_dev *pdev)
5154
{
5255
switch (pdev->device) {
5356
case OC_DEVICE_ID1:
5457
return OC_NAME;
5558
case OC_DEVICE_ID2:
56-
return OC_NAME1;
59+
return OC_NAME_BE;
60+
case OC_DEVICE_ID3:
61+
return OC_NAME_LANCER;
5762
case BE_DEVICE_ID2:
5863
return BE3_NAME;
5964
default:
@@ -149,6 +154,7 @@ struct be_eq_obj {
149154
u16 min_eqd; /* in usecs */
150155
u16 max_eqd; /* in usecs */
151156
u16 cur_eqd; /* in usecs */
157+
u8 msix_vec_idx;
152158

153159
struct napi_struct napi;
154160
};
@@ -260,6 +266,8 @@ struct be_adapter {
260266
u32 num_rx_qs;
261267
u32 big_page_size; /* Compounded page size shared by rx wrbs */
262268

269+
u8 msix_vec_next_idx;
270+
263271
struct vlan_group *vlan_grp;
264272
u16 vlans_added;
265273
u16 max_vlans; /* Number of vlans supported */
@@ -299,8 +307,8 @@ struct be_adapter {
299307

300308
bool sriov_enabled;
301309
struct be_vf_cfg vf_cfg[BE_MAX_VF];
302-
u8 base_eq_id;
303310
u8 is_virtfn;
311+
u32 sli_family;
304312
};
305313

306314
#define be_physfn(adapter) (!adapter->is_virtfn)
@@ -309,6 +317,8 @@ struct be_adapter {
309317
#define BE_GEN2 2
310318
#define BE_GEN3 3
311319

320+
#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3)
321+
312322
extern const struct ethtool_ops be_ethtool_ops;
313323

314324
#define tx_stats(adapter) (&adapter->tx_stats)
@@ -416,10 +426,17 @@ static inline u8 is_udp_pkt(struct sk_buff *skb)
416426
static inline void be_check_sriov_fn_type(struct be_adapter *adapter)
417427
{
418428
u8 data;
419-
420-
pci_write_config_byte(adapter->pdev, 0xFE, 0xAA);
421-
pci_read_config_byte(adapter->pdev, 0xFE, &data);
422-
adapter->is_virtfn = (data != 0xAA);
429+
u32 sli_intf;
430+
431+
if (lancer_chip(adapter)) {
432+
pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET,
433+
&sli_intf);
434+
adapter->is_virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0;
435+
} else {
436+
pci_write_config_byte(adapter->pdev, 0xFE, 0xAA);
437+
pci_read_config_byte(adapter->pdev, 0xFE, &data);
438+
adapter->is_virtfn = (data != 0xAA);
439+
}
423440
}
424441

425442
static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)

‎drivers/net/benet/be_cmds.c

Lines changed: 73 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -323,7 +323,12 @@ static int be_mbox_notify_wait(struct be_adapter *adapter)
323323

324324
static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
325325
{
326-
u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
326+
u32 sem;
327+
328+
if (lancer_chip(adapter))
329+
sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
330+
else
331+
sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
327332

328333
*stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
329334
if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
@@ -465,14 +470,25 @@ int be_cmd_fw_init(struct be_adapter *adapter)
465470
spin_lock(&adapter->mbox_lock);
466471

467472
wrb = (u8 *)wrb_from_mbox(adapter);
468-
*wrb++ = 0xFF;
469-
*wrb++ = 0x12;
470-
*wrb++ = 0x34;
471-
*wrb++ = 0xFF;
472-
*wrb++ = 0xFF;
473-
*wrb++ = 0x56;
474-
*wrb++ = 0x78;
475-
*wrb = 0xFF;
473+
if (lancer_chip(adapter)) {
474+
*wrb++ = 0xFF;
475+
*wrb++ = 0x34;
476+
*wrb++ = 0x12;
477+
*wrb++ = 0xFF;
478+
*wrb++ = 0xFF;
479+
*wrb++ = 0x78;
480+
*wrb++ = 0x56;
481+
*wrb = 0xFF;
482+
} else {
483+
*wrb++ = 0xFF;
484+
*wrb++ = 0x12;
485+
*wrb++ = 0x34;
486+
*wrb++ = 0xFF;
487+
*wrb++ = 0xFF;
488+
*wrb++ = 0x56;
489+
*wrb++ = 0x78;
490+
*wrb = 0xFF;
491+
}
476492

477493
status = be_mbox_notify_wait(adapter);
478494

@@ -680,16 +696,36 @@ int be_cmd_cq_create(struct be_adapter *adapter,
680696
OPCODE_COMMON_CQ_CREATE, sizeof(*req));
681697

682698
req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
699+
if (lancer_chip(adapter)) {
700+
req->hdr.version = 1;
701+
req->page_size = 1; /* 1 for 4K */
702+
AMAP_SET_BITS(struct amap_cq_context_lancer, coalescwm, ctxt,
703+
coalesce_wm);
704+
AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
705+
no_delay);
706+
AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
707+
__ilog2_u32(cq->len/256));
708+
AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
709+
AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
710+
ctxt, 1);
711+
AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
712+
ctxt, eq->id);
713+
AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
714+
} else {
715+
AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
716+
coalesce_wm);
717+
AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
718+
ctxt, no_delay);
719+
AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
720+
__ilog2_u32(cq->len/256));
721+
AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
722+
AMAP_SET_BITS(struct amap_cq_context_be, solevent,
723+
ctxt, sol_evts);
724+
AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
725+
AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
726+
AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
727+
}
683728

684-
AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
685-
AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
686-
AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
687-
__ilog2_u32(cq->len/256));
688-
AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
689-
AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
690-
AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
691-
AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
692-
AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
693729
be_dws_cpu_to_le(ctxt, sizeof(req->context));
694730

695731
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
@@ -737,13 +773,27 @@ int be_cmd_mccq_create(struct be_adapter *adapter,
737773
OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
738774

739775
req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
776+
if (lancer_chip(adapter)) {
777+
req->hdr.version = 1;
778+
req->cq_id = cpu_to_le16(cq->id);
779+
780+
AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
781+
be_encoded_q_len(mccq->len));
782+
AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
783+
AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
784+
ctxt, cq->id);
785+
AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
786+
ctxt, 1);
787+
788+
} else {
789+
AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
790+
AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
791+
be_encoded_q_len(mccq->len));
792+
AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
793+
}
740794

741-
AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
742-
AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
743-
be_encoded_q_len(mccq->len));
744-
AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
745795
/* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
746-
req->async_event_bitmap[0] |= 0x00000022;
796+
req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
747797
be_dws_cpu_to_le(ctxt, sizeof(req->context));
748798

749799
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);

‎drivers/net/benet/be_cmds.h

Lines changed: 36 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -309,7 +309,7 @@ struct be_cmd_req_pmac_del {
309309
/******************** Create CQ ***************************/
310310
/* Pseudo amap definition in which each bit of the actual structure is defined
311311
* as a byte: used to calculate offset/shift/mask of each field */
312-
struct amap_cq_context {
312+
struct amap_cq_context_be {
313313
u8 cidx[11]; /* dword 0*/
314314
u8 rsvd0; /* dword 0*/
315315
u8 coalescwm[2]; /* dword 0*/
@@ -332,14 +332,32 @@ struct amap_cq_context {
332332
u8 rsvd5[32]; /* dword 3*/
333333
} __packed;
334334

335+
struct amap_cq_context_lancer {
336+
u8 rsvd0[12]; /* dword 0*/
337+
u8 coalescwm[2]; /* dword 0*/
338+
u8 nodelay; /* dword 0*/
339+
u8 rsvd1[12]; /* dword 0*/
340+
u8 count[2]; /* dword 0*/
341+
u8 valid; /* dword 0*/
342+
u8 rsvd2; /* dword 0*/
343+
u8 eventable; /* dword 0*/
344+
u8 eqid[16]; /* dword 1*/
345+
u8 rsvd3[15]; /* dword 1*/
346+
u8 armed; /* dword 1*/
347+
u8 rsvd4[32]; /* dword 2*/
348+
u8 rsvd5[32]; /* dword 3*/
349+
} __packed;
350+
335351
struct be_cmd_req_cq_create {
336352
struct be_cmd_req_hdr hdr;
337353
u16 num_pages;
338-
u16 rsvd0;
339-
u8 context[sizeof(struct amap_cq_context) / 8];
354+
u8 page_size;
355+
u8 rsvd0;
356+
u8 context[sizeof(struct amap_cq_context_be) / 8];
340357
struct phys_addr pages[8];
341358
} __packed;
342359

360+
343361
struct be_cmd_resp_cq_create {
344362
struct be_cmd_resp_hdr hdr;
345363
u16 cq_id;
@@ -349,7 +367,7 @@ struct be_cmd_resp_cq_create {
349367
/******************** Create MCCQ ***************************/
350368
/* Pseudo amap definition in which each bit of the actual structure is defined
351369
* as a byte: used to calculate offset/shift/mask of each field */
352-
struct amap_mcc_context {
370+
struct amap_mcc_context_be {
353371
u8 con_index[14];
354372
u8 rsvd0[2];
355373
u8 ring_size[4];
@@ -364,12 +382,23 @@ struct amap_mcc_context {
364382
u8 rsvd2[32];
365383
} __packed;
366384

385+
struct amap_mcc_context_lancer {
386+
u8 async_cq_id[16];
387+
u8 ring_size[4];
388+
u8 rsvd0[12];
389+
u8 rsvd1[31];
390+
u8 valid;
391+
u8 async_cq_valid[1];
392+
u8 rsvd2[31];
393+
u8 rsvd3[32];
394+
} __packed;
395+
367396
struct be_cmd_req_mcc_create {
368397
struct be_cmd_req_hdr hdr;
369398
u16 num_pages;
370-
u16 rsvd0;
399+
u16 cq_id;
371400
u32 async_event_bitmap[1];
372-
u8 context[sizeof(struct amap_mcc_context) / 8];
401+
u8 context[sizeof(struct amap_mcc_context_be) / 8];
373402
struct phys_addr pages[8];
374403
} __packed;
375404

@@ -605,6 +634,7 @@ struct be_hw_stats {
605634
struct be_rxf_stats rxf;
606635
u32 rsvd[48];
607636
struct be_erx_stats erx;
637+
u32 rsvd1[6];
608638
};
609639

610640
struct be_cmd_req_get_stats {

‎drivers/net/benet/be_hw.h

Lines changed: 35 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,10 +32,12 @@
3232
#define MPU_EP_CONTROL 0
3333

3434
/********** MPU semphore ******************/
35-
#define MPU_EP_SEMAPHORE_OFFSET 0xac
36-
#define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
37-
#define EP_SEMAPHORE_POST_ERR_MASK 0x1
38-
#define EP_SEMAPHORE_POST_ERR_SHIFT 31
35+
#define MPU_EP_SEMAPHORE_OFFSET 0xac
36+
#define MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET 0x400
37+
#define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
38+
#define EP_SEMAPHORE_POST_ERR_MASK 0x1
39+
#define EP_SEMAPHORE_POST_ERR_SHIFT 31
40+
3941
/* MPU semphore POST stage values */
4042
#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
4143
#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
@@ -66,13 +68,38 @@
6668
#define PCICFG_UE_STATUS_LOW_MASK 0xA8
6769
#define PCICFG_UE_STATUS_HI_MASK 0xAC
6870

71+
/******** SLI_INTF ***********************/
72+
#define SLI_INTF_REG_OFFSET 0x58
73+
#define SLI_INTF_VALID_MASK 0xE0000000
74+
#define SLI_INTF_VALID 0xC0000000
75+
#define SLI_INTF_HINT2_MASK 0x1F000000
76+
#define SLI_INTF_HINT2_SHIFT 24
77+
#define SLI_INTF_HINT1_MASK 0x00FF0000
78+
#define SLI_INTF_HINT1_SHIFT 16
79+
#define SLI_INTF_FAMILY_MASK 0x00000F00
80+
#define SLI_INTF_FAMILY_SHIFT 8
81+
#define SLI_INTF_IF_TYPE_MASK 0x0000F000
82+
#define SLI_INTF_IF_TYPE_SHIFT 12
83+
#define SLI_INTF_REV_MASK 0x000000F0
84+
#define SLI_INTF_REV_SHIFT 4
85+
#define SLI_INTF_FT_MASK 0x00000001
86+
87+
88+
/* SLI family */
89+
#define BE_SLI_FAMILY 0x0
90+
#define LANCER_A0_SLI_FAMILY 0xA
91+
92+
6993
/********* ISR0 Register offset **********/
7094
#define CEV_ISR0_OFFSET 0xC18
7195
#define CEV_ISR_SIZE 4
7296

7397
/********* Event Q door bell *************/
7498
#define DB_EQ_OFFSET DB_CQ_OFFSET
7599
#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
100+
#define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
101+
#define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
102+
76103
/* Clear the interrupt for this eq */
77104
#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
78105
/* Must be 1 */
@@ -85,6 +112,10 @@
85112
/********* Compl Q door bell *************/
86113
#define DB_CQ_OFFSET 0x120
87114
#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
115+
#define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
116+
#define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
117+
placing at 11-15 */
118+
88119
/* Number of event entries processed */
89120
#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
90121
/* Rearm bit */

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