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Add support for sub*f3vfp and add*f3vfp
As done before for mul and div let's use extern "C" to generate `"aapcs"` or `"aapcs-vfp"` depending on target configuration.
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4 files changed

+67
-4
lines changed

4 files changed

+67
-4
lines changed

README.md

Lines changed: 4 additions & 4 deletions
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@@ -85,8 +85,8 @@ features = ["c"]
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- [x] adddf3.c
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- [x] addsf3.c
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- [ ] arm/adddf3vfp.S
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- [ ] arm/addsf3vfp.S
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- [x] arm/adddf3vfp.S
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- [x] arm/addsf3vfp.S
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- [ ] arm/aeabi_dcmp.S
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- [ ] arm/aeabi_fcmp.S
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- [x] arm/aeabi_idivmod.S
@@ -127,8 +127,8 @@ features = ["c"]
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- [ ] arm/negsf2vfp.S
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- [ ] arm/nesf2vfp.S
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- [ ] arm/softfloat-alias.list
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- [ ] arm/subdf3vfp.S
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- [ ] arm/subsf3vfp.S
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- [x] arm/subdf3vfp.S
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- [x] arm/subsf3vfp.S
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- [ ] arm/truncdfsf2vfp.S
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- [ ] arm/udivmodsi4.S (generic version is done)
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- [ ] arm/udivsi3.S (generic version is done)

src/float/add.rs

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@@ -193,4 +193,14 @@ intrinsics! {
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pub extern "C" fn __adddf3(a: f64, b: f64) -> f64 {
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add(a, b)
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}
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#[cfg(target_arch = "arm")]
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pub extern "C" fn __addsf3vfp(a: f32, b: f32) -> f32 {
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a + b
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}
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#[cfg(target_arch = "arm")]
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pub extern "C" fn __adddf3vfp(a: f64, b: f64) -> f64 {
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a + b
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}
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}

src/float/sub.rs

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Original file line numberDiff line numberDiff line change
@@ -10,4 +10,14 @@ intrinsics! {
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pub extern "C" fn __subdf3(a: f64, b: f64) -> f64 {
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a + f64::from_repr(b.repr() ^ f64::SIGN_MASK)
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}
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#[cfg(target_arch = "arm")]
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pub extern "C" fn __subsf3vfp(a: f32, b: f32) -> f32 {
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a - b
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}
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#[cfg(target_arch = "arm")]
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pub extern "C" fn __subdf3vfp(a: f64, b: f64) -> f64 {
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a - b
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}
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}

testcrate/build.rs

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@@ -51,6 +51,28 @@ fn main() {
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},
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"compiler_builtins::float::add::__addsf3(a, b)");
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if target_arch_arm {
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gen(|(a, b): (MyF64, MyF64)| {
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let c = a.0 + b.0;
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if a.0.is_nan() || b.0.is_nan() || c.is_nan() {
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None
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} else {
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Some(c)
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}
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},
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"compiler_builtins::float::add::__adddf3vfp(a, b)");
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gen(|(a, b): (LargeF32, LargeF32)| {
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let c = a.0 + b.0;
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if a.0.is_nan() || b.0.is_nan() || c.is_nan() {
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None
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} else {
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Some(c)
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}
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},
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"compiler_builtins::float::add::__addsf3vfp(a, b)");
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}
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// float/cmp.rs
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gen(|(a, b): (MyF64, MyF64)| {
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let (a, b) = (a.0, b.0);
@@ -209,6 +231,27 @@ fn main() {
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},
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"compiler_builtins::float::sub::__subsf3(a, b)");
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if target_arch_arm {
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gen(|(a, b): (MyF64, MyF64)| {
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let c = a.0 - b.0;
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if a.0.is_nan() || b.0.is_nan() || c.is_nan() {
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None
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} else {
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Some(c)
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}
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},
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"compiler_builtins::float::sub::__subdf3vfp(a, b)");
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gen(|(a, b): (LargeF32, LargeF32)| {
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let c = a.0 - b.0;
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if a.0.is_nan() || b.0.is_nan() || c.is_nan() {
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None
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} else {
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Some(c)
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}
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},
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"compiler_builtins::float::sub::__subsf3vfp(a, b)");
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}
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// float/mul.rs
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gen(|(a, b): (MyF64, MyF64)| {
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let c = a.0 * b.0;

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