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Optimize access to thread local cache.
This patch saves one CPU instruction on each "_tsrm_ls_cache" access in ZTS CLI/CGI/FPM builds. This reduce typical instruction sequence for EG(current_execute_data) access from 4 to 3 CPU instructions.
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2 files changed

+18
-2
lines changed

2 files changed

+18
-2
lines changed

TSRM/TSRM.h

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,14 @@ TSRM_API const char *tsrm_api_name(void);
143143
# define TSRM_TLS __thread
144144
#endif
145145

146+
#if !defined(__has_attribute) || !__has_attribute(tls_model)
147+
# define TSRM_TLS_MODEL_ATTR
148+
#elif __PIC__
149+
# define TSRM_TLS_MODEL_ATTR __attribute__((tls_model("initial-exec")))
150+
#else
151+
# define TSRM_TLS_MODEL_ATTR __attribute__((tls_model("local-exec")))
152+
#endif
153+
146154
#define TSRM_SHUFFLE_RSRC_ID(rsrc_id) ((rsrc_id)+1)
147155
#define TSRM_UNSHUFFLE_RSRC_ID(rsrc_id) ((rsrc_id)-1)
148156

@@ -155,8 +163,8 @@ TSRM_API const char *tsrm_api_name(void);
155163
#define TSRMG_BULK_STATIC(id, type) ((type) (*((void ***) TSRMLS_CACHE))[TSRM_UNSHUFFLE_RSRC_ID(id)])
156164
#define TSRMG_FAST_STATIC(offset, type, element) (TSRMG_FAST_BULK_STATIC(offset, type)->element)
157165
#define TSRMG_FAST_BULK_STATIC(offset, type) ((type) (((char*) TSRMLS_CACHE)+(offset)))
158-
#define TSRMLS_CACHE_EXTERN() extern TSRM_TLS void *TSRMLS_CACHE;
159-
#define TSRMLS_CACHE_DEFINE() TSRM_TLS void *TSRMLS_CACHE = NULL;
166+
#define TSRMLS_CACHE_EXTERN() extern TSRM_TLS void *TSRMLS_CACHE TSRM_TLS_MODEL_ATTR;
167+
#define TSRMLS_CACHE_DEFINE() TSRM_TLS void *TSRMLS_CACHE TSRM_TLS_MODEL_ATTR = NULL;
160168
#define TSRMLS_CACHE_UPDATE() TSRMLS_CACHE = tsrm_get_ls_cache()
161169
#define TSRMLS_CACHE _tsrm_ls_cache
162170

ext/opcache/jit/zend_jit_x86.dasc

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2366,13 +2366,21 @@ static int zend_jit_setup(void)
23662366
# elif defined(__GNUC__) && defined(__x86_64__)
23672367
tsrm_ls_cache_tcb_offset = tsrm_get_ls_cache_tcb_offset();
23682368
if (tsrm_ls_cache_tcb_offset == 0) {
2369+
#if defined(__has_attribute) && __has_attribute(tls_model)
2370+
size_t ret;
2371+
2372+
asm ("movq _tsrm_ls_cache@gottpoff(%%rip),%0"
2373+
: "=r" (ret));
2374+
tsrm_ls_cache_tcb_offset = ret;
2375+
#else
23692376
size_t *ti;
23702377

23712378
__asm__(
23722379
"leaq _tsrm_ls_cache@tlsgd(%%rip), %0\n"
23732380
: "=a" (ti));
23742381
tsrm_tls_offset = ti[1];
23752382
tsrm_tls_index = ti[0] * 16;
2383+
#endif
23762384
}
23772385
# elif defined(__GNUC__) && defined(__i386__)
23782386
tsrm_ls_cache_tcb_offset = tsrm_get_ls_cache_tcb_offset();

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