@@ -680,7 +680,8 @@ def acc_ops_batch_norm(
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@tensorrt_converter (acc_ops .layer_norm )
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def acc_ops_layer_norm (network , target , args , kwargs , name ):
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return add_layer_norm (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .softmax )
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def acc_ops_softmax (
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network : TRTNetwork ,
@@ -731,7 +732,8 @@ def acc_ops_tile(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_tile (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .sign )
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def acc_ops_sign (
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network : TRTNetwork ,
@@ -760,6 +762,7 @@ def acc_ops_relu(
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_relu (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .leaky_relu )
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def acc_ops_leaky_relu (
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network : TRTNetwork ,
@@ -769,7 +772,8 @@ def acc_ops_leaky_relu(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_leaky_relu (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .elu )
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def acc_ops_elu (
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network : TRTNetwork ,
@@ -779,7 +783,8 @@ def acc_ops_elu(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_elu (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .selu )
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def acc_ops_selu (
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network : TRTNetwork ,
@@ -790,6 +795,7 @@ def acc_ops_selu(
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_selu (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .softsign )
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def acc_ops_softsign (
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network : TRTNetwork ,
@@ -799,7 +805,8 @@ def acc_ops_softsign(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_softsign (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .sin )
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def acc_ops_sin (
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network : TRTNetwork ,
@@ -875,6 +882,7 @@ def acc_ops_tanh(
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_tanh (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .asin )
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def acc_ops_asin (
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network : TRTNetwork ,
@@ -1191,7 +1199,8 @@ def acc_ops_maximum(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_maximum (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .minimum )
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def acc_ops_minimum (
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network : TRTNetwork ,
@@ -1201,7 +1210,8 @@ def acc_ops_minimum(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_minimum (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .dtype )
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def acc_ops_dtype (
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network : TRTNetwork ,
@@ -1271,6 +1281,7 @@ def acc_ops_logical_and(
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_logical_and (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .ne , no_implicit_batch_dim = True )
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def acc_ops_ne (
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network : TRTNetwork ,
@@ -1280,7 +1291,8 @@ def acc_ops_ne(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_ne (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .eq , no_implicit_batch_dim = True )
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def acc_ops_eq (
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network : TRTNetwork ,
@@ -1290,7 +1302,8 @@ def acc_ops_eq(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_eq (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .gt , no_implicit_batch_dim = True )
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def acc_ops_gt (
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network : TRTNetwork ,
@@ -1300,7 +1313,8 @@ def acc_ops_gt(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_gt (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .lt , no_implicit_batch_dim = True )
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def acc_ops_lt (
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network : TRTNetwork ,
@@ -1310,7 +1324,7 @@ def acc_ops_lt(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_lt (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .logical_or , no_implicit_batch_dim = True )
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def acc_ops_logical_or (
@@ -1321,7 +1335,8 @@ def acc_ops_logical_or(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_logical_or (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .logical_xor , no_implicit_batch_dim = True )
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def acc_ops_logical_xor (
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network : TRTNetwork ,
@@ -1331,7 +1346,8 @@ def acc_ops_logical_xor(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_logical_xor (network , target , kwargs , name )
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# T113156424 Have some accuracy problems in hf_T5.
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# [TRT] [W] Weights [name=isinf_1_inf_t]: Converted FP32 value in weights (either FP32 infinity or FP32 value outside FP16 range) to corresponding FP16 infinity. If this is not the desired behavior, please modify the weights or retrain with regularization to reduce the magnitude of the weights.
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# @tensorrt_converter(acc_ops.isinf)
@@ -1425,6 +1441,7 @@ def acc_ops_fmod(
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_fmod (network , target , kwargs , name )
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# T113156424 embedding implemenatation is very limited and shows no usage in hf models due to the indices are int64.
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# if we cast to int32, it will create accuracy issues. We'd better leave it to future implementation.
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# @tensorrt_converter(acc_ops.embedding, no_implicit_batch_dim=True)
@@ -1653,6 +1670,7 @@ def acc_ops_add(
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_add (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .sub )
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def acc_ops_sub (
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network : TRTNetwork ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_sub (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .div )
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def acc_ops_div (
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network : TRTNetwork ,
@@ -1673,6 +1692,7 @@ def acc_ops_div(
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_div (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .floor_div )
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def acc_ops_floor_div (
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network : TRTNetwork ,
@@ -1682,7 +1702,8 @@ def acc_ops_floor_div(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_floor_div (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .trunc_div )
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def acc_ops_trunc_div (
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network : TRTNetwork ,
@@ -1692,7 +1713,8 @@ def acc_ops_trunc_div(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_trunc_div (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .mul )
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def acc_ops_mul (
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network : TRTNetwork ,
@@ -1702,7 +1724,8 @@ def acc_ops_mul(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_mul (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .pow )
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def acc_ops_pow (
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network : TRTNetwork ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_pow (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .unsqueeze )
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def acc_ops_unsqueeze (
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network : TRTNetwork ,
@@ -1982,7 +2006,7 @@ def acc_ops_slice_tensor(
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_slice (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .expand )
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def acc_ops_expand_tensor (
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_expand (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .where )
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def acc_ops_where (
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_linear (network , target , kwargs , name )
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def add_clamp (network , input , val , op , name ):
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if not len (input .shape ):
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# clamping scalar
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_matmul (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .hardsigmoid )
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def acc_ops_hard_sigmoid (
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network : TRTNetwork ,
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_gelu (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .chunk )
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def acc_ops_chunk (
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name : str ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_cumsum (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .hardtanh )
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def acc_ops_hardtanh (
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network : TRTNetwork ,
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) -> Union [TRTTensor , Sequence [TRTTensor ]]:
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return add_hardtanh (network , target , kwargs , name )
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@tensorrt_converter (acc_ops .interpolate )
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def acc_ops_interpolate (
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network : TRTNetwork ,
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