[Execuotrch][cpuinfo] Add util to find out # of performant cores

This helps with identifying the # of performant cores which will later be used
when reseting the threadpool or using the guard to figure out how many threads
should be used

Differential Revision: [D54766068](https://our.internmc.facebook.com/intern/diff/D54766068/)

ghstack-source-id: 218209329
Pull Request resolved: #2350

Author: kimishpatel

backends/xnnpack/threadpool/cpuinfo_utils.cpp

@@ -0,0 +1,134 @@
+#include <executorch/runtime/platform/assert.h>
+#include <fstream>
+#include <iostream>
+#include <mutex>
+#include <string>
+#include <vector>
+
+#include "cpuinfo_utils.h"
+
+namespace torch {
+namespace executorch {
+namespace cpuinfo {
+
+// Ignore revisions (last digit (4 LSBs))
+#define CPUINFO_ARM_MIDR_CORTEX_A520 UINT32_C(0x410FD800)
+#define CPUINFO_ARM_MIDR_CORTEX_A53 UINT32_C(0x410FD030)
+#define CPUINFO_ARM_MIDR_CORTEX_A55 UINT32_C(0x410FD050)
+#define CPUINFO_ARM_MIDR_CORTEX_A57 UINT32_C(0x410FD070)
+
+#define RIVISION_MASK UINT32_C(0xFFFFFFF0)
+
+namespace {
+bool is_non_performant_core(const struct cpuinfo_uarch_info* uarch_info) {
+  switch (uarch_info->uarch) {
+    case cpuinfo_uarch_cortex_a55:
+    case cpuinfo_uarch_cortex_a53:
+    case cpuinfo_uarch_cortex_a510:
+      return true;
+    // This can be so many other cores.
+    // Need to update this to better account for slow cores
+    // Also does not account Apple's A/M series cores
+    // And not yet qcomm's
+    default:
+      break;
+  }
+    // A520 is not yet updated in cpuinfo
+    // Hence decode it separately.
+#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
+  if ((uarch_info->midr & RIVISION_MASK) == CPUINFO_ARM_MIDR_CORTEX_A520) {
+    return true;
+  }
+#endif
+  return false;
+}
+
+std::vector<uint32_t>* get_static_cpu_midr_vector() {
+  static std::vector<uint32_t> cpu_midrs;
+  return &cpu_midrs;
+}
+
+bool populate_available_cpu_mids() {
+  std::vector<uint32_t>* cpu_midrs = get_static_cpu_midr_vector();
+  uint32_t num_possible_cores = cpuinfo_get_processors_count();
+  cpu_midrs->resize(num_possible_cores);
+  const std::string kMidrFilePathPrefix = "/sys/devices/system/cpu/cpu";
+  const std::string kMidrFilePathSuffix = "/regs/identification/midr_el1";
+  for (int32_t i = 0; i < num_possible_cores; ++i) {
+    std::string midr_file_path =
+        kMidrFilePathPrefix + std::to_string(i) + kMidrFilePathSuffix;
+    ET_LOG(Info, "Reading file %s", midr_file_path.c_str());
+    std::fstream midr_file(midr_file_path, std::ios_base::in);
+    uint32_t tmp{0};
+    if (midr_file.is_open()) {
+      std::string x;
+      std::getline(midr_file, x);
+      tmp = std::stoi(x, nullptr, 16);
+      (*cpu_midrs)[i] = tmp;
+    } else {
+      ET_LOG(Info, "Failed to open midr file %s", midr_file_path.c_str());
+      cpu_midrs->clear();
+      return false;
+    }
+  }
+  return true;
+}
+
+uint32_t _get_num_performant_cores() {
+  static std::once_flag flag;
+  std::call_once(flag, []() { populate_available_cpu_mids(); });
+  std::vector<uint32_t>* cpu_midrs = get_static_cpu_midr_vector();
+  uint32_t num_possible_cores = cpuinfo_get_processors_count();
+  if (num_possible_cores != cpu_midrs->size()) {
+    ET_LOG(Info, "CPU info and manual query on # of cpus dont match.");
+    return 0;
+  }
+  for (int32_t i = 0; i < cpu_midrs->size(); ++i) {
+    uint32_t masked_midr = (*cpu_midrs)[i] & RIVISION_MASK;
+    switch (masked_midr) {
+      case CPUINFO_ARM_MIDR_CORTEX_A520:
+      case CPUINFO_ARM_MIDR_CORTEX_A53:
+      case CPUINFO_ARM_MIDR_CORTEX_A55:
+      case CPUINFO_ARM_MIDR_CORTEX_A57:
+        num_possible_cores--;
+        break;
+      default:
+        break;
+    }
+  }
+  return num_possible_cores;
+}
+
+} // namespace
+
+uint32_t get_num_performant_cores() {
+  ET_CHECK_MSG(cpuinfo_initialize(), "cpuinfo cannot be initialized.");
+  const uint32_t uarch_count = cpuinfo_get_uarchs_count();
+  uint32_t num_possible_cores = cpuinfo_get_processors_count();
+  uint32_t num_non_performant_core = 0;
+  if (uarch_count > 1) {
+    for (int32_t i = 0; i < uarch_count; ++i) {
+      const struct cpuinfo_uarch_info* uarch_info = cpuinfo_get_uarch(i);
+      if (is_non_performant_core(uarch_info)) {
+        num_non_performant_core += uarch_info->processor_count;
+      }
+    }
+    ET_LOG(Info, "Number of efficient cores %d", num_non_performant_core);
+    if (num_possible_cores <= num_non_performant_core) {
+      ET_LOG(
+          Info, "Total number of cores must be larger than efficient cores.");
+      return 0;
+    }
+    return (num_possible_cores - num_non_performant_core);
+  } else {
+    // Something seems wrong. Lets check each processor's midr
+    // In one plua 12 while it has 2 little cores, the topology
+    // reported in /sys/devices/system/cpu/cpu* /topology/core_siblings_list
+    // report wrong topology which results in wront configratuon
+    return _get_num_performant_cores();
+  }
+}
+
+} // namespace cpuinfo
+} // namespace executorch
+} // namespace torch

backends/xnnpack/threadpool/cpuinfo_utils.h

@@ -0,0 +1,13 @@
+#pragma once
+
+#include <cpuinfo.h>
+
+namespace torch {
+namespace executorch {
+namespace cpuinfo {
+
+uint32_t get_num_performant_cores();
+
+} // namespace cpuinfo
+} // namespace executorch
+} // namespace torch

backends/xnnpack/threadpool/targets.bzl

@@ -40,3 +40,27 @@ def define_common_targets():
             "@EXECUTORCH_CLIENTS",
         ],
     )
+
+    runtime.cxx_library(
+        name = "cpuinfo_utils",
+        srcs = [
+            "cpuinfo_utils.cpp",
+        ],
+        deps = [
+            "//executorch/runtime/core:core",
+        ],
+        exported_headers = [
+            "cpuinfo_utils.h",
+        ],
+        exported_deps = [
+            third_party_dep("pthreadpool"),
+            third_party_dep("cpuinfo"),
+        ],
+        visibility = [
+            "//executorch/...",
+            "//executorch/backends/...",
+            "//executorch/runtime/backend/...",
+            "//executorch/extension/threadpool/test/...",
+            "@EXECUTORCH_CLIENTS",
+        ],
+    )