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Arm backend: Use better Ethos-U PMU counters for Ethos-U85
Differential Revision: D65147935 Pull Request resolved: #6455
1 parent cd565b5 commit 63ff1ae

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2 files changed

+24
-9
lines changed

2 files changed

+24
-9
lines changed
Submodule ethos-u-core-driver updated from 90f9df9 to 78df000

examples/arm/executor_runner/arm_perf_monitor.cpp

Lines changed: 23 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,14 @@ static std::vector<uint64_t> ethosu_pmuEventCounts(
2424
ETHOSU_PMU_Get_NumEventCounters(),
2525
0);
2626

27+
#if defined(ETHOSU55) || defined(ETHOSU65)
2728
static const uint32_t ethosu_pmuCountersUsed = 4;
29+
#elif defined(ETHOSU85)
30+
static const uint32_t ethosu_pmuCountersUsed = 5;
31+
#else
32+
#error No NPU target defined
33+
#endif
34+
2835
// ethosu_pmuCountersUsed should match numbers of counters setup in
2936
// ethosu_inference_begin() and not be more then the HW supports
3037
static_assert(ETHOSU_PMU_NCOUNTERS >= ethosu_pmuCountersUsed);
@@ -44,18 +51,26 @@ void ethosu_inference_begin(struct ethosu_driver* drv, void*) {
4451
ETHOSU_PMU_Set_EVTYPER(drv, 1, ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED);
4552
ETHOSU_PMU_Set_EVTYPER(drv, 2, ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN);
4653
ETHOSU_PMU_Set_EVTYPER(drv, 3, ETHOSU_PMU_NPU_IDLE);
54+
// Enable the 4 counters
55+
ETHOSU_PMU_CNTR_Enable(
56+
drv,
57+
ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CNT2_Msk | ETHOSU_PMU_CNT3_Msk |
58+
ETHOSU_PMU_CNT4_Msk);
4759
#elif defined(ETHOSU85)
48-
ETHOSU_PMU_Set_EVTYPER(drv, 0, ETHOSU_PMU_EXT0_RD_DATA_BEAT_RECEIVED);
49-
ETHOSU_PMU_Set_EVTYPER(drv, 1, ETHOSU_PMU_EXT1_RD_DATA_BEAT_RECEIVED);
50-
ETHOSU_PMU_Set_EVTYPER(drv, 2, ETHOSU_PMU_EXT0_WR_DATA_BEAT_WRITTEN);
51-
ETHOSU_PMU_Set_EVTYPER(drv, 3, ETHOSU_PMU_NPU_IDLE);
60+
ETHOSU_PMU_Set_EVTYPER(drv, 0, ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED);
61+
ETHOSU_PMU_Set_EVTYPER(drv, 1, ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN);
62+
ETHOSU_PMU_Set_EVTYPER(drv, 2, ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED);
63+
ETHOSU_PMU_Set_EVTYPER(drv, 3, ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN);
64+
ETHOSU_PMU_Set_EVTYPER(drv, 4, ETHOSU_PMU_NPU_IDLE);
65+
// Enable the 5 counters
66+
ETHOSU_PMU_CNTR_Enable(
67+
drv,
68+
ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CNT2_Msk | ETHOSU_PMU_CNT3_Msk |
69+
ETHOSU_PMU_CNT4_Msk | ETHOSU_PMU_CNT5_Msk);
5270
#else
5371
#error No NPU target defined
5472
#endif
5573

56-
// Enable 4 counters
57-
ETHOSU_PMU_CNTR_Enable(drv, 0xf);
58-
5974
ETHOSU_PMU_CNTR_Enable(drv, ETHOSU_PMU_CCNT_Msk);
6075
ETHOSU_PMU_CYCCNT_Reset(drv);
6176

@@ -177,7 +192,7 @@ void StopMeasurements() {
177192
#elif defined(ETHOSU85)
178193
ET_LOG(
179194
Info,
180-
"Ethos-U PMU Events:[ETHOSU_PMU_EXT0_RD_DATA_BEAT_RECEIVED, ETHOSU_PMU_EXT1_RD_DATA_BEAT_RECEIVED, ETHOSU_PMU_EXT0_WR_DATA_BEAT_WRITTEN, ETHOSU_PMU_NPU_IDLE]");
195+
"Ethos-U PMU Events:[ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED, ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN, ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED, ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN, ETHOSU_PMU_NPU_IDLE]");
181196
#else
182197
#error No NPU target defined
183198
#endif

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