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Qualcomm AI Egine Direct -- add ssg2115p (#5867)
Summary: Pull Request resolved: #5867 Reviewed By: kirklandsign Differential Revision: D63878338 Pulled By: cccclai fbshipit-source-id: 2e6f6c14f4d15c54f874ef1ea52cae1ac609b5e1
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backends/qualcomm/serialization/qnn_compile_spec_schema.py

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@@ -33,6 +33,7 @@ class QcomChipset(IntEnum):
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SM8450 = 36 # v69
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SM8475 = 42 # v69
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SM8550 = 43 # v73
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SSG2115P = 46 # v73
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SM8650 = 57 # v75
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@@ -47,6 +48,7 @@ class SocInfo:
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QcomChipset.SM8475: SocInfo(QcomChipset.SM8475, HtpInfo(HtpArch.V69, 8)),
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QcomChipset.SM8550: SocInfo(QcomChipset.SM8550, HtpInfo(HtpArch.V73, 8)),
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QcomChipset.SM8650: SocInfo(QcomChipset.SM8650, HtpInfo(HtpArch.V75, 8)),
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QcomChipset.SSG2115P: SocInfo(QcomChipset.SSG2115P, HtpInfo(HtpArch.V73, 2)),
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}
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backends/qualcomm/serialization/schema.fbs

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@@ -32,6 +32,7 @@ enum QcomChipset: int {
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SM8450 = 36,
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SM8475 = 42,
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SM8550 = 43,
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SSG2115P = 46,
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SM8650 = 57,
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}
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@@ -170,7 +171,7 @@ table QnnExecuTorchOptions {
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/// Profiling level of the delegate and the backend. Default is off.
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profile_level:QnnExecuTorchProfileLevel;
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/// Enables usage of shared buffer between application and backend for graph I/O.
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shared_buffer:bool;
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backends/qualcomm/tests/utils.py

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@@ -118,6 +118,7 @@ class TestQNN(unittest.TestCase):
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model: QcomChipset = None
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compiler_specs: List[CompileSpec] = None
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arch_table = {
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"SSG2115P": QcomChipset.SSG2115P,
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"SM8650": QcomChipset.SM8650,
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"SM8550": QcomChipset.SM8550,
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"SM8475": QcomChipset.SM8475,

examples/qualcomm/oss_scripts/llama2/llama.py

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@@ -48,6 +48,7 @@
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soc_to_chipset_map = {
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"SSG2115P": QcomChipset.SSG2115P,
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"SM8650": QcomChipset.SM8650,
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"SM8550": QcomChipset.SM8550,
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"SM8475": QcomChipset.SM8475,

examples/qualcomm/utils.py

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@@ -83,6 +83,7 @@ def __init__(
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self.debug_output_path = f"{self.workspace}/debug_output.bin"
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self.output_folder = f"{self.workspace}/outputs"
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self.arch_table = {
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"SSG2115P": "73",
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"SM8650": "75",
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"SM8550": "73",
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"SM8475": "69",

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