Use auto-generated hardware/structs/ headers (based off SVD) SVD errors fixed.

Author: kilograham

src/rp2040/hardware_regs/include/hardware/platform_defs.h

@@ -28,10 +28,11 @@
 #define NUM_UARTS _u(2)
 #define NUM_I2CS _u(2)
 #define NUM_SPIS _u(2)
-
+#define NUM_TIMERS _u(4)
 #define NUM_ADC_CHANNELS _u(5)
 
 #define NUM_BANK0_GPIOS _u(30)
+#define NUM_QSPI_GPIOS _u(6)
 
 #define PIO_INSTRUCTION_COUNT _u(32)
 

src/rp2040/hardware_structs/include/hardware/structs/adc.h

@@ -1,27 +1,90 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_ADC_H
 #define _HARDWARE_STRUCTS_ADC_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/adc.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(ADC_CS_OFFSET) // ADC_CS
+    // ADC Control and Status
+    // 0x001f0000 [20:16] : RROBIN (0): Round-robin sampling
+    // 0x00007000 [14:12] : AINSEL (0): Select analog mux input
+    // 0x00000400 [10]    : ERR_STICKY (0): Some past ADC conversion encountered an error
+    // 0x00000200 [9]     : ERR (0): The most recent ADC conversion encountered an error; result is undefined or noisy
+    // 0x00000100 [8]     : READY (0): 1 if the ADC is ready to start a new conversion
+    // 0x00000008 [3]     : START_MANY (0): Continuously perform conversions whilst this bit is 1
+    // 0x00000004 [2]     : START_ONCE (0): Start a single conversion
+    // 0x00000002 [1]     : TS_EN (0): Power on temperature sensor
+    // 0x00000001 [0]     : EN (0): Power on ADC and enable its clock
     io_rw_32 cs;
-    io_rw_32 result;
+
+    _REG_(ADC_RESULT_OFFSET) // ADC_RESULT
+    // Result of most recent ADC conversion
+    // 0x00000fff [11:0]  : RESULT (0)
+    io_ro_32 result;
+
+    _REG_(ADC_FCS_OFFSET) // ADC_FCS
+    // FIFO control and status
+    // 0x0f000000 [27:24] : THRESH (0): DREQ/IRQ asserted when level >= threshold
+    // 0x000f0000 [19:16] : LEVEL (0): The number of conversion results currently waiting in the FIFO
+    // 0x00000800 [11]    : OVER (0): 1 if the FIFO has been overflowed
+    // 0x00000400 [10]    : UNDER (0): 1 if the FIFO has been underflowed
+    // 0x00000200 [9]     : FULL (0)
+    // 0x00000100 [8]     : EMPTY (0)
+    // 0x00000008 [3]     : DREQ_EN (0): If 1: assert DMA requests when FIFO contains data
+    // 0x00000004 [2]     : ERR (0): If 1: conversion error bit appears in the FIFO alongside the result
+    // 0x00000002 [1]     : SHIFT (0): If 1: FIFO results are right-shifted to be one byte in size
+    // 0x00000001 [0]     : EN (0): If 1: write result to the FIFO after each conversion
     io_rw_32 fcs;
-    io_rw_32 fifo;
+
+    _REG_(ADC_FIFO_OFFSET) // ADC_FIFO
+    // Conversion result FIFO
+    // 0x00008000 [15]    : ERR (0): 1 if this particular sample experienced a conversion error
+    // 0x00000fff [11:0]  : VAL (0)
+    io_ro_32 fifo;
+
+    _REG_(ADC_DIV_OFFSET) // ADC_DIV
+    // Clock divider
+    // 0x00ffff00 [23:8]  : INT (0): Integer part of clock divisor
+    // 0x000000ff [7:0]   : FRAC (0): Fractional part of clock divisor
     io_rw_32 div;
-    io_rw_32 intr;
+
+    _REG_(ADC_INTR_OFFSET) // ADC_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_ro_32 intr;
+
+    _REG_(ADC_INTE_OFFSET) // ADC_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
     io_rw_32 inte;
+
+    _REG_(ADC_INTF_OFFSET) // ADC_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
     io_rw_32 intf;
-    io_rw_32 ints;
-} adc_hw_t;
 
-check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET);
+    _REG_(ADC_INTS_OFFSET) // ADC_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_ro_32 ints;
+} adc_hw_t;
 
 #define adc_hw ((adc_hw_t *const)ADC_BASE)
 

src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h

@@ -1,14 +1,25 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_BUS_CTRL_H
 #define _HARDWARE_STRUCTS_BUS_CTRL_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/busctrl.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 enum bus_ctrl_perf_counter {
     arbiter_rom_perf_event_access = 19,
     arbiter_rom_perf_event_access_contested = 18,
@@ -33,15 +44,33 @@ enum bus_ctrl_perf_counter {
 };
 
 typedef struct {
+    _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
+    // Bus fabric performance counter 0
+    // 0x00ffffff [23:0]  : PERFCTR0 (0): Busfabric saturating performance counter 0
+    io_rw_32 value;
+
+    _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
+    // Bus fabric performance event select for PERFCTR0
+    // 0x0000001f [4:0]   : PERFSEL0 (0x1f): Select an event for PERFCTR0
+    io_rw_32 sel;
+} bus_ctrl_perf_hw_t;
+
+typedef struct {
+    _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
+    // Set the priority of each master for bus arbitration
+    // 0x00001000 [12]    : DMA_W (0): 0 - low priority, 1 - high priority
+    // 0x00000100 [8]     : DMA_R (0): 0 - low priority, 1 - high priority
+    // 0x00000010 [4]     : PROC1 (0): 0 - low priority, 1 - high priority
+    // 0x00000001 [0]     : PROC0 (0): 0 - low priority, 1 - high priority
     io_rw_32 priority;
+
+    _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
+    // Bus priority acknowledge
+    // 0x00000001 [0]     : BUS_PRIORITY_ACK (0): Goes to 1 once all arbiters have registered the new global priority levels
     io_ro_32 priority_ack;
-    struct {
-        io_rw_32 value;
-        io_rw_32 sel;
-    } counter[4];
-} bus_ctrl_hw_t;
 
-check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET);
+    bus_ctrl_perf_hw_t counter[4];
+} bus_ctrl_hw_t;
 
 #define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE)