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lurchlurch
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Updated reg_headers and SVD (#612)
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+45
-30
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3 files changed

+45
-30
lines changed

‎src/rp2040/hardware_regs/include/hardware/regs/dma.h

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5056,7 +5056,7 @@
50565056
#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000)
50575057
#define DMA_CH0_DBG_CTDREQ_MSB _u(5)
50585058
#define DMA_CH0_DBG_CTDREQ_LSB _u(0)
5059-
#define DMA_CH0_DBG_CTDREQ_ACCESS "RO"
5059+
#define DMA_CH0_DBG_CTDREQ_ACCESS "WC"
50605060
// =============================================================================
50615061
// Register : DMA_CH0_DBG_TCR
50625062
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5078,7 +5078,7 @@
50785078
#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000)
50795079
#define DMA_CH1_DBG_CTDREQ_MSB _u(5)
50805080
#define DMA_CH1_DBG_CTDREQ_LSB _u(0)
5081-
#define DMA_CH1_DBG_CTDREQ_ACCESS "RO"
5081+
#define DMA_CH1_DBG_CTDREQ_ACCESS "WC"
50825082
// =============================================================================
50835083
// Register : DMA_CH1_DBG_TCR
50845084
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5100,7 +5100,7 @@
51005100
#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000)
51015101
#define DMA_CH2_DBG_CTDREQ_MSB _u(5)
51025102
#define DMA_CH2_DBG_CTDREQ_LSB _u(0)
5103-
#define DMA_CH2_DBG_CTDREQ_ACCESS "RO"
5103+
#define DMA_CH2_DBG_CTDREQ_ACCESS "WC"
51045104
// =============================================================================
51055105
// Register : DMA_CH2_DBG_TCR
51065106
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5122,7 +5122,7 @@
51225122
#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000)
51235123
#define DMA_CH3_DBG_CTDREQ_MSB _u(5)
51245124
#define DMA_CH3_DBG_CTDREQ_LSB _u(0)
5125-
#define DMA_CH3_DBG_CTDREQ_ACCESS "RO"
5125+
#define DMA_CH3_DBG_CTDREQ_ACCESS "WC"
51265126
// =============================================================================
51275127
// Register : DMA_CH3_DBG_TCR
51285128
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5144,7 +5144,7 @@
51445144
#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000)
51455145
#define DMA_CH4_DBG_CTDREQ_MSB _u(5)
51465146
#define DMA_CH4_DBG_CTDREQ_LSB _u(0)
5147-
#define DMA_CH4_DBG_CTDREQ_ACCESS "RO"
5147+
#define DMA_CH4_DBG_CTDREQ_ACCESS "WC"
51485148
// =============================================================================
51495149
// Register : DMA_CH4_DBG_TCR
51505150
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5166,7 +5166,7 @@
51665166
#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000)
51675167
#define DMA_CH5_DBG_CTDREQ_MSB _u(5)
51685168
#define DMA_CH5_DBG_CTDREQ_LSB _u(0)
5169-
#define DMA_CH5_DBG_CTDREQ_ACCESS "RO"
5169+
#define DMA_CH5_DBG_CTDREQ_ACCESS "WC"
51705170
// =============================================================================
51715171
// Register : DMA_CH5_DBG_TCR
51725172
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5188,7 +5188,7 @@
51885188
#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000)
51895189
#define DMA_CH6_DBG_CTDREQ_MSB _u(5)
51905190
#define DMA_CH6_DBG_CTDREQ_LSB _u(0)
5191-
#define DMA_CH6_DBG_CTDREQ_ACCESS "RO"
5191+
#define DMA_CH6_DBG_CTDREQ_ACCESS "WC"
51925192
// =============================================================================
51935193
// Register : DMA_CH6_DBG_TCR
51945194
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5210,7 +5210,7 @@
52105210
#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000)
52115211
#define DMA_CH7_DBG_CTDREQ_MSB _u(5)
52125212
#define DMA_CH7_DBG_CTDREQ_LSB _u(0)
5213-
#define DMA_CH7_DBG_CTDREQ_ACCESS "RO"
5213+
#define DMA_CH7_DBG_CTDREQ_ACCESS "WC"
52145214
// =============================================================================
52155215
// Register : DMA_CH7_DBG_TCR
52165216
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5232,7 +5232,7 @@
52325232
#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000)
52335233
#define DMA_CH8_DBG_CTDREQ_MSB _u(5)
52345234
#define DMA_CH8_DBG_CTDREQ_LSB _u(0)
5235-
#define DMA_CH8_DBG_CTDREQ_ACCESS "RO"
5235+
#define DMA_CH8_DBG_CTDREQ_ACCESS "WC"
52365236
// =============================================================================
52375237
// Register : DMA_CH8_DBG_TCR
52385238
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5254,7 +5254,7 @@
52545254
#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000)
52555255
#define DMA_CH9_DBG_CTDREQ_MSB _u(5)
52565256
#define DMA_CH9_DBG_CTDREQ_LSB _u(0)
5257-
#define DMA_CH9_DBG_CTDREQ_ACCESS "RO"
5257+
#define DMA_CH9_DBG_CTDREQ_ACCESS "WC"
52585258
// =============================================================================
52595259
// Register : DMA_CH9_DBG_TCR
52605260
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5276,7 +5276,7 @@
52765276
#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000)
52775277
#define DMA_CH10_DBG_CTDREQ_MSB _u(5)
52785278
#define DMA_CH10_DBG_CTDREQ_LSB _u(0)
5279-
#define DMA_CH10_DBG_CTDREQ_ACCESS "RO"
5279+
#define DMA_CH10_DBG_CTDREQ_ACCESS "WC"
52805280
// =============================================================================
52815281
// Register : DMA_CH10_DBG_TCR
52825282
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@@ -5298,7 +5298,7 @@
52985298
#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000)
52995299
#define DMA_CH11_DBG_CTDREQ_MSB _u(5)
53005300
#define DMA_CH11_DBG_CTDREQ_LSB _u(0)
5301-
#define DMA_CH11_DBG_CTDREQ_ACCESS "RO"
5301+
#define DMA_CH11_DBG_CTDREQ_ACCESS "WC"
53025302
// =============================================================================
53035303
// Register : DMA_CH11_DBG_TCR
53045304
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length

‎src/rp2040/hardware_regs/include/hardware/regs/usb.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1012,7 +1012,7 @@
10121012
#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000)
10131013
#define USB_SIE_STATUS_CONNECTED_MSB _u(16)
10141014
#define USB_SIE_STATUS_CONNECTED_LSB _u(16)
1015-
#define USB_SIE_STATUS_CONNECTED_ACCESS "RO"
1015+
#define USB_SIE_STATUS_CONNECTED_ACCESS "WC"
10161016
// -----------------------------------------------------------------------------
10171017
// Field : USB_SIE_STATUS_RESUME
10181018
// Description : Host: Device has initiated a remote resume. Device: host has
@@ -1037,7 +1037,7 @@
10371037
#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300)
10381038
#define USB_SIE_STATUS_SPEED_MSB _u(9)
10391039
#define USB_SIE_STATUS_SPEED_LSB _u(8)
1040-
#define USB_SIE_STATUS_SPEED_ACCESS "RO"
1040+
#define USB_SIE_STATUS_SPEED_ACCESS "WC"
10411041
// -----------------------------------------------------------------------------
10421042
// Field : USB_SIE_STATUS_SUSPENDED
10431043
// Description : Bus in suspended state. Valid for device and host. Host and
@@ -1047,7 +1047,7 @@
10471047
#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010)
10481048
#define USB_SIE_STATUS_SUSPENDED_MSB _u(4)
10491049
#define USB_SIE_STATUS_SUSPENDED_LSB _u(4)
1050-
#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO"
1050+
#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC"
10511051
// -----------------------------------------------------------------------------
10521052
// Field : USB_SIE_STATUS_LINE_STATE
10531053
// Description : USB bus line state

‎src/rp2040/hardware_regs/rp2040.svd

Lines changed: 30 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -33403,8 +33403,9 @@
3340333403
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3340433404
<fields>
3340533405
<field>
33406-
<access>read-only</access>
33406+
<access>read-write</access>
3340733407
<bitRange>[5:0]</bitRange>
33408+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3340833409
<name>CH0_DBG_CTDREQ</name>
3340933410
</field>
3341033411
</fields>
@@ -33423,8 +33424,9 @@
3342333424
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3342433425
<fields>
3342533426
<field>
33426-
<access>read-only</access>
33427+
<access>read-write</access>
3342733428
<bitRange>[5:0]</bitRange>
33429+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3342833430
<name>CH1_DBG_CTDREQ</name>
3342933431
</field>
3343033432
</fields>
@@ -33443,8 +33445,9 @@
3344333445
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3344433446
<fields>
3344533447
<field>
33446-
<access>read-only</access>
33448+
<access>read-write</access>
3344733449
<bitRange>[5:0]</bitRange>
33450+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3344833451
<name>CH2_DBG_CTDREQ</name>
3344933452
</field>
3345033453
</fields>
@@ -33463,8 +33466,9 @@
3346333466
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3346433467
<fields>
3346533468
<field>
33466-
<access>read-only</access>
33469+
<access>read-write</access>
3346733470
<bitRange>[5:0]</bitRange>
33471+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3346833472
<name>CH3_DBG_CTDREQ</name>
3346933473
</field>
3347033474
</fields>
@@ -33483,8 +33487,9 @@
3348333487
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3348433488
<fields>
3348533489
<field>
33486-
<access>read-only</access>
33490+
<access>read-write</access>
3348733491
<bitRange>[5:0]</bitRange>
33492+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3348833493
<name>CH4_DBG_CTDREQ</name>
3348933494
</field>
3349033495
</fields>
@@ -33503,8 +33508,9 @@
3350333508
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3350433509
<fields>
3350533510
<field>
33506-
<access>read-only</access>
33511+
<access>read-write</access>
3350733512
<bitRange>[5:0]</bitRange>
33513+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3350833514
<name>CH5_DBG_CTDREQ</name>
3350933515
</field>
3351033516
</fields>
@@ -33523,8 +33529,9 @@
3352333529
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3352433530
<fields>
3352533531
<field>
33526-
<access>read-only</access>
33532+
<access>read-write</access>
3352733533
<bitRange>[5:0]</bitRange>
33534+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3352833535
<name>CH6_DBG_CTDREQ</name>
3352933536
</field>
3353033537
</fields>
@@ -33543,8 +33550,9 @@
3354333550
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3354433551
<fields>
3354533552
<field>
33546-
<access>read-only</access>
33553+
<access>read-write</access>
3354733554
<bitRange>[5:0]</bitRange>
33555+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3354833556
<name>CH7_DBG_CTDREQ</name>
3354933557
</field>
3355033558
</fields>
@@ -33563,8 +33571,9 @@
3356333571
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3356433572
<fields>
3356533573
<field>
33566-
<access>read-only</access>
33574+
<access>read-write</access>
3356733575
<bitRange>[5:0]</bitRange>
33576+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3356833577
<name>CH8_DBG_CTDREQ</name>
3356933578
</field>
3357033579
</fields>
@@ -33583,8 +33592,9 @@
3358333592
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3358433593
<fields>
3358533594
<field>
33586-
<access>read-only</access>
33595+
<access>read-write</access>
3358733596
<bitRange>[5:0]</bitRange>
33597+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3358833598
<name>CH9_DBG_CTDREQ</name>
3358933599
</field>
3359033600
</fields>
@@ -33603,8 +33613,9 @@
3360333613
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3360433614
<fields>
3360533615
<field>
33606-
<access>read-only</access>
33616+
<access>read-write</access>
3360733617
<bitRange>[5:0]</bitRange>
33618+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3360833619
<name>CH10_DBG_CTDREQ</name>
3360933620
</field>
3361033621
</fields>
@@ -33623,8 +33634,9 @@
3362333634
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
3362433635
<fields>
3362533636
<field>
33626-
<access>read-only</access>
33637+
<access>read-write</access>
3362733638
<bitRange>[5:0]</bitRange>
33639+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
3362833640
<name>CH11_DBG_CTDREQ</name>
3362933641
</field>
3363033642
</fields>
@@ -40061,9 +40073,10 @@
4006140073
<name>SETUP_REC</name>
4006240074
</field>
4006340075
<field>
40064-
<access>read-only</access>
40076+
<access>read-write</access>
4006540077
<bitRange>[16:16]</bitRange>
4006640078
<description>Device: connected</description>
40079+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
4006740080
<name>CONNECTED</name>
4006840081
</field>
4006940082
<field>
@@ -40080,15 +40093,17 @@
4008040093
<name>VBUS_OVER_CURR</name>
4008140094
</field>
4008240095
<field>
40083-
<access>read-only</access>
40096+
<access>read-write</access>
4008440097
<bitRange>[9:8]</bitRange>
4008540098
<description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description>
40099+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
4008640100
<name>SPEED</name>
4008740101
</field>
4008840102
<field>
40089-
<access>read-only</access>
40103+
<access>read-write</access>
4009040104
<bitRange>[4:4]</bitRange>
4009140105
<description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
40106+
<modifiedWriteValues>oneToClear</modifiedWriteValues>
4009240107
<name>SUSPENDED</name>
4009340108
</field>
4009440109
<field>

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