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[AArch64] Introduce new armv9.6 features (llvm#111677)
This patch implements new features introduced in 2024 release of ARM ISA and creates predicates, which will be used by new instructions. Co-authored-by: Caroline Concatto [email protected] Co-authored-by: Spencer Abson [email protected]
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‎clang/test/Driver/aarch64-v96a.c

Lines changed: 39 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,14 +6,50 @@
66
// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A %s
77
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A %s
88
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A %s
9-
// GENERICV96A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"
9+
// GENERICV96A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+cmpbr"{{.*}} "-target-feature" "+fprcvt"{{.*}} "-target-feature" "+sve2p2"
1010

1111
// RUN: %clang -target aarch64_be -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
1212
// RUN: %clang -target aarch64_be -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
1313
// RUN: %clang -target aarch64 -mbig-endian -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
1414
// RUN: %clang -target aarch64 -mbig-endian -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
1515
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
1616
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
17-
// GENERICV96A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"
18-
//
17+
// GENERICV96A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+cmpbr"{{.*}} "-target-feature" "+fprcvt"{{.*}} "-target-feature" "+sve2p2"
18+
1919
// ===== Features supported on aarch64 =====
20+
21+
// RUN: %clang -target aarch64 -march=armv9.6a+f8f16mm -### -c %s 2>&1 | FileCheck -check-prefix=V96A-F8F16MM %s
22+
// RUN: %clang -target aarch64 -march=armv9.6-a+f8f16mm -### -c %s 2>&1 | FileCheck -check-prefix=V96A-F8F16MM %s
23+
// V96A-F8F16MM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+f8f16mm"
24+
25+
// RUN: %clang -target aarch64 -march=armv9.6a+f8f32mm -### -c %s 2>&1 | FileCheck -check-prefix=V96A-F8F32MM %s
26+
// RUN: %clang -target aarch64 -march=armv9.6-a+f8f32mm -### -c %s 2>&1 | FileCheck -check-prefix=V96A-F8F32MM %s
27+
// V96A-F8F32MM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+f8f32mm"
28+
29+
// RUN: %clang -target aarch64 -march=armv9.6a+lsfe -### -c %s 2>&1 | FileCheck -check-prefix=V96A-LSFE %s
30+
// RUN: %clang -target aarch64 -march=armv9.6-a+lsfe -### -c %s 2>&1 | FileCheck -check-prefix=V96A-LSFE %s
31+
// V96A-LSFE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+lsfe"
32+
33+
// RUN: %clang -target aarch64 -march=armv9.6a+sme2p2 -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SME2p2 %s
34+
// RUN: %clang -target aarch64 -march=armv9.6-a+sme2p2 -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SME2p2 %s
35+
// V96A-SME2p2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+sme2p2"
36+
37+
// RUN: %clang -target aarch64 -march=armv9.6a+ssve-aes -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SSVE-AES %s
38+
// RUN: %clang -target aarch64 -march=armv9.6-a+ssve-aes -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SSVE-AES %s
39+
// V96A-SSVE-AES: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+ssve-aes"
40+
41+
// RUN: %clang -target aarch64 -march=armv9.6a+sve2p2 -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SVE2p2 %s
42+
// RUN: %clang -target aarch64 -march=armv9.6-a+sve2p2 -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SVE2p2 %s
43+
// V96A-SVE2p2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+sve2p2"
44+
45+
// RUN: %clang -target aarch64 -march=armv9.6a+sve-aes2 -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SVE-AES2 %s
46+
// RUN: %clang -target aarch64 -march=armv9.6-a+sve-aes2 -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SVE-AES2 %s
47+
// V96A-SVE-AES2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+sve-aes2"
48+
49+
// RUN: %clang -target aarch64 -march=armv9.6a+sve-bfscale -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SVE-BFSCALE %s
50+
// RUN: %clang -target aarch64 -march=armv9.6-a+sve-bfscale -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SVE-BFSCALE %s
51+
// V96A-SVE-BFSCALE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+sve-bfscale"
52+
53+
// RUN: %clang -target aarch64 -march=armv9.6a+sve-f16f32mm -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SVE-F16F32MM %s
54+
// RUN: %clang -target aarch64 -march=armv9.6-a+sve-f16f32mm -### -c %s 2>&1 | FileCheck -check-prefix=V96A-SVE-F16F32MM %s
55+
// V96A-SVE-F16F32MM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+sve-f16f32mm"

‎clang/test/Driver/print-supported-extensions-aarch64.c

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
// CHECK-NEXT: bf16 FEAT_BF16 Enable BFloat16 Extension
99
// CHECK-NEXT: brbe FEAT_BRBE Enable Branch Record Buffer Extension
1010
// CHECK-NEXT: bti FEAT_BTI Enable Branch Target Identification
11+
// CHECK-NEXT: cmpbr FEAT_CMPBR Enable Armv9.6-A base compare and branch instructions
1112
// CHECK-NEXT: fcma FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
1213
// CHECK-NEXT: cpa FEAT_CPA Enable Armv9.5-A Checked Pointer Arithmetic
1314
// CHECK-NEXT: crc FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
@@ -18,6 +19,8 @@
1819
// CHECK-NEXT: dotprod FEAT_DotProd Enable dot product support
1920
// CHECK-NEXT: f32mm FEAT_F32MM Enable Matrix Multiply FP32 Extension
2021
// CHECK-NEXT: f64mm FEAT_F64MM Enable Matrix Multiply FP64 Extension
22+
// CHECK-NEXT: f8f16mm FEAT_F8F16MM Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication
23+
// CHECK-NEXT: f8f32mm FEAT_F8F32MM Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication
2124
// CHECK-NEXT: faminmax FEAT_FAMINMAX Enable FAMIN and FAMAX instructions
2225
// CHECK-NEXT: flagm FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
2326
// CHECK-NEXT: fp FEAT_FP Enable Armv8.0-A Floating Point Extensions
@@ -26,6 +29,7 @@
2629
// CHECK-NEXT: fp8dot2 FEAT_FP8DOT2 Enable FP8 2-way dot instructions
2730
// CHECK-NEXT: fp8dot4 FEAT_FP8DOT4 Enable FP8 4-way dot instructions
2831
// CHECK-NEXT: fp8fma FEAT_FP8FMA Enable Armv9.5-A FP8 multiply-add instructions
32+
// CHECK-NEXT: fprcvt FEAT_FPRCVT Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of different input and output sizes
2933
// CHECK-NEXT: fp16 FEAT_FP16 Enable half-precision floating-point data processing
3034
// CHECK-NEXT: gcs FEAT_GCS Enable Armv9.4-A Guarded Call Stack Extension
3135
// CHECK-NEXT: hbc FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension
@@ -35,6 +39,7 @@
3539
// CHECK-NEXT: ls64 FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension
3640
// CHECK-NEXT: lse FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
3741
// CHECK-NEXT: lse128 FEAT_LSE128 Enable Armv9.4-A 128-bit Atomic instructions
42+
// CHECK-NEXT: lsfe FEAT_LSFE Enable Armv9.6-A base Atomic floating-point in-memory instructions
3843
// CHECK-NEXT: lut FEAT_LUT Enable Lookup Table instructions
3944
// CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
4045
// CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
@@ -64,20 +69,26 @@
6469
// CHECK-NEXT: sme-lutv2 FEAT_SME_LUTv2 Enable Scalable Matrix Extension (SME) LUTv2 instructions
6570
// CHECK-NEXT: sme2 FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions
6671
// CHECK-NEXT: sme2p1 FEAT_SME2p1 Enable Scalable Matrix Extension 2.1 instructions
72+
// CHECK-NEXT: sme2p2 FEAT_SME2p2 Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions
6773
// CHECK-NEXT: profile FEAT_SPE Enable Statistical Profiling extension
6874
// CHECK-NEXT: predres2 FEAT_SPECRES2 Enable Speculation Restriction Instruction
6975
// CHECK-NEXT: ssbs FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
76+
// CHECK-NEXT: ssve-aes FEAT_SSVE_AES Enable Armv9.6-A SVE2 AES support in streaming SVE mode
7077
// CHECK-NEXT: ssve-fp8dot2 FEAT_SSVE_FP8DOT2 Enable SVE2 FP8 2-way dot product instructions
7178
// CHECK-NEXT: ssve-fp8dot4 FEAT_SSVE_FP8DOT4 Enable SVE2 FP8 4-way dot product instructions
7279
// CHECK-NEXT: ssve-fp8fma FEAT_SSVE_FP8FMA Enable SVE2 FP8 multiply-add instructions
7380
// CHECK-NEXT: sve FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
81+
// CHECK-NEXT: sve-aes2 FEAT_SVE_AES2 Enable Armv9.6-A SVE multi-vector AES and 128-bit PMULL instructions
7482
// CHECK-NEXT: sve-b16b16 FEAT_SVE_B16B16 Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions
83+
// CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE Enable Armv9.6-A SVE BFloat16 scaling instructions
84+
// CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply
7585
// CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
7686
// CHECK-NEXT: sve2-aes FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable AES SVE2 instructions
7787
// CHECK-NEXT: sve2-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
7888
// CHECK-NEXT: sve2-sha3 FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
7989
// CHECK-NEXT: sve2-sm4 FEAT_SVE_SM4 Enable SM4 SVE2 instructions
8090
// CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
91+
// CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions
8192
// CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension
8293
// CHECK-NEXT: tlbiw FEAT_TLBIW Enable Armv9.5-A TLBI VMALL for Dirty State
8394
// CHECK-NEXT: tme FEAT_TME Enable Transactional Memory Extension

‎llvm/lib/Target/AArch64/AArch64Features.td

Lines changed: 35 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -522,6 +522,39 @@ def FeatureTLBIW : ExtensionWithMArch<"tlbiw", "TLBIW", "FEAT_TLBIW",
522522
// Armv9.6 Architecture Extensions
523523
//===----------------------------------------------------------------------===//
524524

525+
def FeatureCMPBR : ExtensionWithMArch<"cmpbr", "CMPBR", "FEAT_CMPBR",
526+
"Enable Armv9.6-A base compare and branch instructions">;
527+
528+
def FeatureF8F32MM: ExtensionWithMArch<"f8f32mm", "F8F32MM", "FEAT_F8F32MM",
529+
"Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication">;
530+
531+
def FeatureF8F16MM: ExtensionWithMArch<"f8f16mm", "F8F16MM", "FEAT_F8F16MM",
532+
"Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication">;
533+
534+
def FeatureFPRCVT: ExtensionWithMArch<"fprcvt", "FPRCVT", "FEAT_FPRCVT",
535+
"Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of"
536+
" different input and output sizes">;
537+
538+
def FeatureLSFE : ExtensionWithMArch<"lsfe", "LSFE", "FEAT_LSFE",
539+
"Enable Armv9.6-A base Atomic floating-point in-memory instructions">;
540+
541+
def FeatureSME2p2: ExtensionWithMArch<"sme2p2", "SME2p2", "FEAT_SME2p2",
542+
"Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions", [FeatureSME2p1]>;
543+
544+
def FeatureSSVE_AES : ExtensionWithMArch<"ssve-aes", "SSVE_AES", "FEAT_SSVE_AES",
545+
"Enable Armv9.6-A SVE2 AES support in streaming SVE mode">;
546+
547+
def FeatureSVE2p2 : ExtensionWithMArch<"sve2p2", "SVE2p2", "FEAT_SVE2p2",
548+
"Enable Armv9.6-A Scalable Vector Extension 2.2 instructions", [FeatureSVE2p1]>;
549+
550+
def FeatureSVEAES2: ExtensionWithMArch<"sve-aes2", "SVE_AES2", "FEAT_SVE_AES2",
551+
"Enable Armv9.6-A SVE multi-vector AES and 128-bit PMULL instructions">;
552+
553+
def FeatureSVEBFSCALE: ExtensionWithMArch<"sve-bfscale", "SVE_BFSCALE", "FEAT_SVE_BFSCALE",
554+
"Enable Armv9.6-A SVE BFloat16 scaling instructions">;
555+
556+
def FeatureSVE_F16F32MM: ExtensionWithMArch<"sve-f16f32mm", "SVE_F16F32MM", "FEAT_SVE_F16F32MM",
557+
"Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions">;
525558

526559
//===----------------------------------------------------------------------===//
527560
// Other Features
@@ -833,8 +866,8 @@ def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a",
833866
[HasV9_4aOps, FeatureCPA],
834867
!listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA, FeatureLUT, FeatureFAMINMAX])>;
835868
def HasV9_6aOps : Architecture64<9, 6, "a", "v9.6a",
836-
[HasV9_5aOps],
837-
!listconcat(HasV9_5aOps.DefaultExts, [])>;
869+
[HasV9_5aOps, FeatureCMPBR, FeatureFPRCVT, FeatureSVE2p2],
870+
!listconcat(HasV9_5aOps.DefaultExts, [FeatureCMPBR, FeatureFPRCVT, FeatureSVE2p2])>;
838871
def HasV8_0rOps : Architecture64<8, 0, "r", "v8r",
839872
[ //v8.1
840873
FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2,

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 34 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -213,12 +213,35 @@ def HasSMEF8F16 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEF8
213213
def HasSMEF8F32 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEF8F32()">,
214214
AssemblerPredicateWithAll<(all_of FeatureSMEF8F32), "sme-f8f32">;
215215

216+
def HasCMPBR : Predicate<"Subtarget->hasCMPBR()">,
217+
AssemblerPredicateWithAll<(all_of FeatureCMPBR), "cmpbr">;
218+
def HasF8F32MM : Predicate<"Subtarget->hasF8F32MM()">,
219+
AssemblerPredicateWithAll<(all_of FeatureF8F32MM), "f8f32mm">;
220+
def HasF8F16MM : Predicate<"Subtarget->hasF8F16MM()">,
221+
AssemblerPredicateWithAll<(all_of FeatureF8F16MM), "f8f16mm">;
222+
def HasFPRCVT : Predicate<"Subtarget->hasFPRCVT()">,
223+
AssemblerPredicateWithAll<(all_of FeatureFPRCVT), "fprcvt">;
224+
def HasLSFE : Predicate<"Subtarget->hasLSFE()">,
225+
AssemblerPredicateWithAll<(all_of FeatureLSFE), "lsfe">;
226+
def HasSME2p2 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSME2p2()">,
227+
AssemblerPredicateWithAll<(all_of FeatureSME2p2), "sme2p2">;
228+
def HasSVEAES2 : Predicate<"Subtarget->hasSVEAES2()">,
229+
AssemblerPredicateWithAll<(all_of FeatureSVEAES2), "sve-aes2">;
230+
def HasSVEBFSCALE : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSVEBFSCALE()">,
231+
AssemblerPredicateWithAll<(all_of FeatureSVEBFSCALE), "sve-bfscale">;
232+
def HasSVE_F16F32MM : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_F16F32MM()">,
233+
AssemblerPredicateWithAll<(all_of FeatureSVE_F16F32MM), "sve-f16f32mm">;
216234
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
217235
// they should be enabled if either has been specified.
218236
def HasSVEorSME
219237
: Predicate<"Subtarget->hasSVE() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
220238
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),
221239
"sve or sme">;
240+
def HasSVEorSME2p2
241+
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
242+
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,
243+
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2),
244+
"sve or sme2p2">;
222245
def HasSVE2orSME
223246
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
224247
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME),
@@ -227,6 +250,10 @@ def HasSVE2orSME2
227250
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
228251
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME2),
229252
"sve2 or sme2">;
253+
def HasSVE2orSSVE_AES
254+
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
255+
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">,
256+
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_AES), "sve2 or ssve-aes">;
230257
def HasSVE2p1_or_HasSME
231258
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
232259
AssemblerPredicateWithAll<(any_of FeatureSME, FeatureSVE2p1), "sme or sve2p1">;
@@ -236,7 +263,13 @@ def HasSVE2p1_or_HasSME2
236263
def HasSVE2p1_or_HasSME2p1
237264
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME2p1())">,
238265
AssemblerPredicateWithAll<(any_of FeatureSME2p1, FeatureSVE2p1), "sme2p1 or sve2p1">;
239-
266+
def HasSVE2p2orSME2p2
267+
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p2() || Subtarget->hasSME2p2())">,
268+
AssemblerPredicateWithAll<(any_of FeatureSME2p2, FeatureSVE2p2), "sme2p2 or sve2p2">;
269+
def HasSVE2p1orSSVE_AES
270+
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2p1()) ||"
271+
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">,
272+
AssemblerPredicateWithAll<(any_of FeatureSVE2p1, FeatureSSVE_AES), "sve2p1 or ssve-aes">;
240273
def HasSMEF16F16orSMEF8F16
241274
: Predicate<"Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16())">,
242275
AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16),

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