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mahesh-attarderlavaee
mahesh-attarde
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rlavaee
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[X86][GlobalISel] Fix RegBank issue for G_FABS (llvm#145674)
Fixes hidden issue in llvm#136718. It removes custom selection code since problem was in RegBank assignment
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+60
-60
lines changed

4 files changed

+60
-60
lines changed

‎llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp

Lines changed: 0 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -95,8 +95,6 @@ class X86InstructionSelector : public InstructionSelector {
9595
MachineFunction &MF) const;
9696
bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
9797
MachineFunction &MF) const;
98-
bool selectFAbs(MachineInstr &I, MachineRegisterInfo &MRI,
99-
MachineFunction &MF) const;
10098
bool selectUAddSub(MachineInstr &I, MachineRegisterInfo &MRI,
10199
MachineFunction &MF) const;
102100
bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI) const;
@@ -393,8 +391,6 @@ bool X86InstructionSelector::select(MachineInstr &I) {
393391
switch (I.getOpcode()) {
394392
default:
395393
return false;
396-
case TargetOpcode::G_FABS:
397-
return selectFAbs(I, MRI, MF);
398394
case TargetOpcode::G_STORE:
399395
case TargetOpcode::G_LOAD:
400396
return selectLoadStoreOp(I, MRI, MF);
@@ -1054,35 +1050,6 @@ bool X86InstructionSelector::selectCmp(MachineInstr &I,
10541050
I.eraseFromParent();
10551051
return true;
10561052
}
1057-
bool X86InstructionSelector::selectFAbs(MachineInstr &I,
1058-
MachineRegisterInfo &MRI,
1059-
MachineFunction &MF) const {
1060-
assert((I.getOpcode() == TargetOpcode::G_FABS) && "unexpected instruction");
1061-
Register SrcReg = I.getOperand(1).getReg();
1062-
Register DstReg = I.getOperand(0).getReg();
1063-
LLT Ty = MRI.getType(SrcReg);
1064-
unsigned OpAbs;
1065-
const TargetRegisterClass *DstRC;
1066-
switch (Ty.getSizeInBits()) {
1067-
default:
1068-
return false;
1069-
case 32:
1070-
OpAbs = X86::ABS_Fp32;
1071-
DstRC = &X86::FR32RegClass;
1072-
break;
1073-
case 64:
1074-
OpAbs = X86::ABS_Fp64;
1075-
DstRC = &X86::FR64RegClass;
1076-
break;
1077-
}
1078-
MRI.setRegClass(DstReg, DstRC);
1079-
MachineInstr &FAbsInst =
1080-
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpAbs), DstReg)
1081-
.addReg(SrcReg);
1082-
constrainSelectedInstRegOperands(FAbsInst, TII, TRI, RBI);
1083-
I.eraseFromParent();
1084-
return true;
1085-
}
10861053

10871054
bool X86InstructionSelector::selectFCmp(MachineInstr &I,
10881055
MachineRegisterInfo &MRI,

‎llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -419,7 +419,8 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
419419
.legalFor(UseX87, {s80});
420420

421421
getActionDefinitionsBuilder(G_FABS)
422-
.legalFor(UseX87 && !HasSSE2 && !HasSSE1, {s64, s80})
422+
.legalFor(UseX87, {s80})
423+
.legalFor(UseX87 && !Is64Bit, {s64})
423424
.lower();
424425

425426
// fp comparison

‎llvm/lib/Target/X86/GISel/X86RegisterBankInfo.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -341,6 +341,7 @@ X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
341341
/* Predicate */ PMI_None, FpRegBank, FpRegBank};
342342
break;
343343
}
344+
case TargetOpcode::G_FABS:
344345
case TargetOpcode::G_TRUNC:
345346
case TargetOpcode::G_ANYEXT: {
346347
auto &Op0 = MI.getOperand(0);
@@ -354,9 +355,9 @@ X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
354355
Ty0.getSizeInBits() == 128 &&
355356
(Ty1.getSizeInBits() == 32 || Ty1.getSizeInBits() == 64) &&
356357
Opc == TargetOpcode::G_ANYEXT;
357-
358-
getInstrPartialMappingIdxs(MI, MRI, /* isFP= */ isFPTrunc || isFPAnyExt,
359-
OpRegBankIdx);
358+
bool isFAbs = (Opc == TargetOpcode::G_FABS);
359+
getInstrPartialMappingIdxs(
360+
MI, MRI, /* isFP= */ isFPTrunc || isFPAnyExt || isFAbs, OpRegBankIdx);
360361
break;
361362
}
362363
case TargetOpcode::G_LOAD: {

‎llvm/test/CodeGen/X86/isel-fabs-x87.ll

Lines changed: 54 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,67 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse | FileCheck %s --check-prefixes=X64
3-
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse -fast-isel | FileCheck %s --check-prefixes=X64
4-
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=X64
5-
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse | FileCheck %s --check-prefixes=X86,SDAG-ISEL
6-
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse -fast-isel | FileCheck %s --check-prefixes=X86,Fast-ISEL
7-
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse -global-isel -global-isel-abort=0 | FileCheck %s --check-prefixes=X86,GISEL-ISEL
2+
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse | FileCheck %s --check-prefixes=X64,SDAG-X64-ISEL
3+
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse -fast-isel | FileCheck %s --check-prefixes=X64,FAST-X64-ISEL
4+
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=X64,GISEL-X64-ISEL
5+
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse | FileCheck %s --check-prefixes=X86,SDAG-X86-ISEL
6+
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse -fast-isel | FileCheck %s --check-prefixes=X86,FAST-X86-ISEL
7+
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse -global-isel -global-isel-abort=0 | FileCheck %s --check-prefixes=X86,GISEL-X86-ISEL
88

99
define void @test_float_abs(ptr %argptr) {
10-
; SDAG-ISEL-LABEL: test_float_abs:
11-
; SDAG-ISEL: # %bb.0:
12-
; SDAG-ISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
13-
; SDAG-ISEL-NEXT: andb $127, 3(%eax)
14-
; SDAG-ISEL-NEXT: retl
15-
;
16-
; Fast-ISEL-LABEL: test_float_abs:
17-
; Fast-ISEL: # %bb.0:
18-
; Fast-ISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
19-
; Fast-ISEL-NEXT: andb $127, 3(%eax)
20-
; Fast-ISEL-NEXT: retl
21-
;
22-
; GISEL-ISEL-LABEL: test_float_abs:
23-
; GISEL-ISEL: # %bb.0:
24-
; GISEL-ISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
25-
; GISEL-ISEL-NEXT: andl $2147483647, (%eax) # imm = 0x7FFFFFFF
26-
; GISEL-ISEL-NEXT: retl
10+
; SDAG-X64-ISEL-LABEL: test_float_abs:
11+
; SDAG-X64-ISEL: # %bb.0:
12+
; SDAG-X64-ISEL-NEXT: andb $127, 3(%rdi)
13+
; SDAG-X64-ISEL-NEXT: retq
14+
;
15+
; FAST-X64-ISEL-LABEL: test_float_abs:
16+
; FAST-X64-ISEL: # %bb.0:
17+
; FAST-X64-ISEL-NEXT: andb $127, 3(%rdi)
18+
; FAST-X64-ISEL-NEXT: retq
19+
;
20+
; GISEL-X64-ISEL-LABEL: test_float_abs:
21+
; GISEL-X64-ISEL: # %bb.0:
22+
; GISEL-X64-ISEL-NEXT: andl $2147483647, (%rdi) # imm = 0x7FFFFFFF
23+
; GISEL-X64-ISEL-NEXT: retq
24+
;
25+
; SDAG-X86-ISEL-LABEL: test_float_abs:
26+
; SDAG-X86-ISEL: # %bb.0:
27+
; SDAG-X86-ISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
28+
; SDAG-X86-ISEL-NEXT: andb $127, 3(%eax)
29+
; SDAG-X86-ISEL-NEXT: retl
30+
;
31+
; FAST-X86-ISEL-LABEL: test_float_abs:
32+
; FAST-X86-ISEL: # %bb.0:
33+
; FAST-X86-ISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
34+
; FAST-X86-ISEL-NEXT: andb $127, 3(%eax)
35+
; FAST-X86-ISEL-NEXT: retl
36+
;
37+
; GISEL-X86-ISEL-LABEL: test_float_abs:
38+
; GISEL-X86-ISEL: # %bb.0:
39+
; GISEL-X86-ISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
40+
; GISEL-X86-ISEL-NEXT: andl $2147483647, (%eax) # imm = 0x7FFFFFFF
41+
; GISEL-X86-ISEL-NEXT: retl
2742
%arg = load float, float* %argptr
2843
%abs = tail call float @llvm.fabs.f32(float %arg)
2944
store float %abs, ptr %argptr
3045
ret void
3146
}
3247

3348
define void @test_double_abs(ptr %argptr) {
49+
; SDAG-X64-ISEL-LABEL: test_double_abs:
50+
; SDAG-X64-ISEL: # %bb.0:
51+
; SDAG-X64-ISEL-NEXT: andb $127, 7(%rdi)
52+
; SDAG-X64-ISEL-NEXT: retq
53+
;
54+
; FAST-X64-ISEL-LABEL: test_double_abs:
55+
; FAST-X64-ISEL: # %bb.0:
56+
; FAST-X64-ISEL-NEXT: andb $127, 7(%rdi)
57+
; FAST-X64-ISEL-NEXT: retq
58+
;
59+
; GISEL-X64-ISEL-LABEL: test_double_abs:
60+
; GISEL-X64-ISEL: # %bb.0:
61+
; GISEL-X64-ISEL-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
62+
; GISEL-X64-ISEL-NEXT: andq %rax, (%rdi)
63+
; GISEL-X64-ISEL-NEXT: retq
64+
;
3465
; X86-LABEL: test_double_abs:
3566
; X86: # %bb.0:
3667
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax

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