@@ -187,20 +187,20 @@ cleanup2343.loopexit4: ; preds = %cleanup1491
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; The test case has been generated by the AMD Fuzzing project and simplified
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; manually and by llvm-reduce.
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- define i32 @constant_phi_leads_to_self_reference () {
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+ define i32 @constant_phi_leads_to_self_reference (ptr %ptr ) {
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; CHECK-LABEL: @constant_phi_leads_to_self_reference(
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- ; CHECK-NEXT: [[A9 :%.*]] = alloca i1, align 1
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+ ; CHECK-NEXT: [[A10 :%.*]] = alloca i1, align 1
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; CHECK-NEXT: br label [[F6:%.*]]
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; CHECK: T3:
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; CHECK-NEXT: [[L6:%.*]] = phi i1 [ [[C4:%.*]], [[BB6:%.*]] ]
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; CHECK-NEXT: br label [[BB5:%.*]]
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; CHECK: BB5:
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- ; CHECK-NEXT: [[L10:%.*]] = load i1, ptr [[A9 ]], align 1
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+ ; CHECK-NEXT: [[L10:%.*]] = load i1, ptr [[A10 ]], align 1
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; CHECK-NEXT: br i1 [[L10]], label [[BB6]], label [[F6]]
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; CHECK: BB6:
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- ; CHECK-NEXT: [[LGV3:%.*]] = load i1, ptr null , align 1
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+ ; CHECK-NEXT: [[LGV3:%.*]] = load i1, ptr [[A7:%.*]] , align 1
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; CHECK-NEXT: [[C4]] = icmp sle i1 [[L6]], true
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- ; CHECK-NEXT: store i1 [[C4]], ptr null , align 1
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+ ; CHECK-NEXT: store i1 [[C4]], ptr [[A7]] , align 1
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; CHECK-NEXT: br i1 [[L6]], label [[F6]], label [[T3:%.*]]
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; CHECK: F6:
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; CHECK-NEXT: ret i32 0
@@ -217,17 +217,17 @@ F1: ; preds = %BB4
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br i1 false , label %T4 , label %T3
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T3: ; preds = %T4, %BB6, %F1
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- %L6 = load i1 , ptr null , align 1
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+ %L6 = load i1 , ptr %ptr , align 1
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br label %BB5
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BB5: ; preds = %F7, %T3
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%L10 = load i1 , ptr %A9 , align 1
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br i1 %L10 , label %BB6 , label %F6
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BB6: ; preds = %BB5
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- %LGV3 = load i1 , ptr null , align 1
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+ %LGV3 = load i1 , ptr %ptr , align 1
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%C4 = icmp sle i1 %L6 , true
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- store i1 %C4 , ptr null , align 1
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+ store i1 %C4 , ptr %ptr , align 1
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br i1 %L6 , label %F6 , label %T3
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T4: ; preds = %F1
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