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[AMDGPU] Remove duplicated/confusing helpers. NFCI (llvm#142598)
Move canGuaranteeTCO and mayTailCallThisCC into AMDGPUBaseInfo instead of keeping two copies for DAG/Global ISel. Also remove isKernelCC, which doesn't agree with isKernel and doesn't seem very useful. While at it, also move all the CC-related helpers into AMDGPUBaseInfo.h and mark them constexpr.
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6 files changed

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-121
lines changed

6 files changed

+85
-121
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Lines changed: 5 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1090,22 +1090,6 @@ bool AMDGPUCallLowering::areCalleeOutgoingArgsTailCallable(
10901090
return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
10911091
}
10921092

1093-
/// Return true if the calling convention is one that we can guarantee TCO for.
1094-
static bool canGuaranteeTCO(CallingConv::ID CC) {
1095-
return CC == CallingConv::Fast;
1096-
}
1097-
1098-
/// Return true if we might ever do TCO for calls with this calling convention.
1099-
static bool mayTailCallThisCC(CallingConv::ID CC) {
1100-
switch (CC) {
1101-
case CallingConv::C:
1102-
case CallingConv::AMDGPU_Gfx:
1103-
return true;
1104-
default:
1105-
return canGuaranteeTCO(CC);
1106-
}
1107-
}
1108-
11091093
bool AMDGPUCallLowering::isEligibleForTailCallOptimization(
11101094
MachineIRBuilder &B, CallLoweringInfo &Info,
11111095
SmallVectorImpl<ArgInfo> &InArgs, SmallVectorImpl<ArgInfo> &OutArgs) const {
@@ -1130,7 +1114,7 @@ bool AMDGPUCallLowering::isEligibleForTailCallOptimization(
11301114
if (!CallerPreserved)
11311115
return false;
11321116

1133-
if (!mayTailCallThisCC(CalleeCC)) {
1117+
if (!AMDGPU::mayTailCallThisCC(CalleeCC)) {
11341118
LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
11351119
return false;
11361120
}
@@ -1144,8 +1128,10 @@ bool AMDGPUCallLowering::isEligibleForTailCallOptimization(
11441128
}
11451129

11461130
// If we have -tailcallopt, then we're done.
1147-
if (MF.getTarget().Options.GuaranteedTailCallOpt)
1148-
return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv();
1131+
if (MF.getTarget().Options.GuaranteedTailCallOpt) {
1132+
return AMDGPU::canGuaranteeTCO(CalleeCC) &&
1133+
CalleeCC == CallerF.getCallingConv();
1134+
}
11491135

11501136
// Verify that the incoming and outgoing arguments from the callee are
11511137
// safe to tail call.

‎llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -125,13 +125,6 @@ void getUsesOfLDSByFunction(const CallGraph &CG, Module &M,
125125
}
126126

127127
bool isKernelLDS(const Function *F) {
128-
// Some weirdness here. AMDGPU::isKernelCC does not call into
129-
// AMDGPU::isKernel with the calling conv, it instead calls into
130-
// isModuleEntryFunction which returns true for more calling conventions
131-
// than AMDGPU::isKernel does. There's a FIXME on AMDGPU::isKernel.
132-
// There's also a test that checks that the LDS lowering does not hit on
133-
// a graphics shader, denoted amdgpu_ps, so stay with the limited case.
134-
// Putting LDS in the name of the function to draw attention to this.
135128
return AMDGPU::isKernel(F->getCallingConv());
136129
}
137130

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -978,7 +978,9 @@ bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
978978

979979
unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
980980
if (auto *Arg = dyn_cast<Argument>(V);
981-
Arg && AMDGPU::isKernelCC(Arg->getParent()) && !Arg->hasByRefAttr())
981+
Arg &&
982+
AMDGPU::isModuleEntryFunctionCC(Arg->getParent()->getCallingConv()) &&
983+
!Arg->hasByRefAttr())
982984
return AMDGPUAS::GLOBAL_ADDRESS;
983985

984986
const auto *LD = dyn_cast<LoadInst>(V);

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 2 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -3574,21 +3574,6 @@ void SITargetLowering::passSpecialInputs(
35743574
}
35753575
}
35763576

3577-
static bool canGuaranteeTCO(CallingConv::ID CC) {
3578-
return CC == CallingConv::Fast;
3579-
}
3580-
3581-
/// Return true if we might ever do TCO for calls with this calling convention.
3582-
static bool mayTailCallThisCC(CallingConv::ID CC) {
3583-
switch (CC) {
3584-
case CallingConv::C:
3585-
case CallingConv::AMDGPU_Gfx:
3586-
return true;
3587-
default:
3588-
return canGuaranteeTCO(CC);
3589-
}
3590-
}
3591-
35923577
bool SITargetLowering::isEligibleForTailCallOptimization(
35933578
SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
35943579
const SmallVectorImpl<ISD::OutputArg> &Outs,
@@ -3597,7 +3582,7 @@ bool SITargetLowering::isEligibleForTailCallOptimization(
35973582
if (AMDGPU::isChainCC(CalleeCC))
35983583
return true;
35993584

3600-
if (!mayTailCallThisCC(CalleeCC))
3585+
if (!AMDGPU::mayTailCallThisCC(CalleeCC))
36013586
return false;
36023587

36033588
// For a divergent call target, we need to do a waterfall loop over the
@@ -3619,7 +3604,7 @@ bool SITargetLowering::isEligibleForTailCallOptimization(
36193604
bool CCMatch = CallerCC == CalleeCC;
36203605

36213606
if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3622-
if (canGuaranteeTCO(CalleeCC) && CCMatch)
3607+
if (AMDGPU::canGuaranteeTCO(CalleeCC) && CCMatch)
36233608
return true;
36243609
return false;
36253610
}

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 0 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -2124,71 +2124,6 @@ bool getHasDepthExport(const Function &F) {
21242124
return F.getFnAttributeAsParsedInteger("amdgpu-depth-export", 0) != 0;
21252125
}
21262126

2127-
bool isShader(CallingConv::ID cc) {
2128-
switch (cc) {
2129-
case CallingConv::AMDGPU_VS:
2130-
case CallingConv::AMDGPU_LS:
2131-
case CallingConv::AMDGPU_HS:
2132-
case CallingConv::AMDGPU_ES:
2133-
case CallingConv::AMDGPU_GS:
2134-
case CallingConv::AMDGPU_PS:
2135-
case CallingConv::AMDGPU_CS_Chain:
2136-
case CallingConv::AMDGPU_CS_ChainPreserve:
2137-
case CallingConv::AMDGPU_CS:
2138-
return true;
2139-
default:
2140-
return false;
2141-
}
2142-
}
2143-
2144-
bool isGraphics(CallingConv::ID cc) {
2145-
return isShader(cc) || cc == CallingConv::AMDGPU_Gfx;
2146-
}
2147-
2148-
bool isCompute(CallingConv::ID cc) {
2149-
return !isGraphics(cc) || cc == CallingConv::AMDGPU_CS;
2150-
}
2151-
2152-
bool isEntryFunctionCC(CallingConv::ID CC) {
2153-
switch (CC) {
2154-
case CallingConv::AMDGPU_KERNEL:
2155-
case CallingConv::SPIR_KERNEL:
2156-
case CallingConv::AMDGPU_VS:
2157-
case CallingConv::AMDGPU_GS:
2158-
case CallingConv::AMDGPU_PS:
2159-
case CallingConv::AMDGPU_CS:
2160-
case CallingConv::AMDGPU_ES:
2161-
case CallingConv::AMDGPU_HS:
2162-
case CallingConv::AMDGPU_LS:
2163-
return true;
2164-
default:
2165-
return false;
2166-
}
2167-
}
2168-
2169-
bool isModuleEntryFunctionCC(CallingConv::ID CC) {
2170-
switch (CC) {
2171-
case CallingConv::AMDGPU_Gfx:
2172-
return true;
2173-
default:
2174-
return isEntryFunctionCC(CC) || isChainCC(CC);
2175-
}
2176-
}
2177-
2178-
bool isChainCC(CallingConv::ID CC) {
2179-
switch (CC) {
2180-
case CallingConv::AMDGPU_CS_Chain:
2181-
case CallingConv::AMDGPU_CS_ChainPreserve:
2182-
return true;
2183-
default:
2184-
return false;
2185-
}
2186-
}
2187-
2188-
bool isKernelCC(const Function *Func) {
2189-
return AMDGPU::isModuleEntryFunctionCC(Func->getCallingConv());
2190-
}
2191-
21922127
bool hasXNACK(const MCSubtargetInfo &STI) {
21932128
return STI.hasFeature(AMDGPU::FeatureXNACK);
21942129
}

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Lines changed: 75 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1306,16 +1306,61 @@ bool getHasColorExport(const Function &F);
13061306
bool getHasDepthExport(const Function &F);
13071307

13081308
LLVM_READNONE
1309-
bool isShader(CallingConv::ID CC);
1309+
constexpr bool isShader(CallingConv::ID CC) {
1310+
switch (CC) {
1311+
case CallingConv::AMDGPU_VS:
1312+
case CallingConv::AMDGPU_LS:
1313+
case CallingConv::AMDGPU_HS:
1314+
case CallingConv::AMDGPU_ES:
1315+
case CallingConv::AMDGPU_GS:
1316+
case CallingConv::AMDGPU_PS:
1317+
case CallingConv::AMDGPU_CS_Chain:
1318+
case CallingConv::AMDGPU_CS_ChainPreserve:
1319+
case CallingConv::AMDGPU_CS:
1320+
return true;
1321+
default:
1322+
return false;
1323+
}
1324+
}
13101325

13111326
LLVM_READNONE
1312-
bool isGraphics(CallingConv::ID CC);
1327+
constexpr bool isGraphics(CallingConv::ID CC) {
1328+
return isShader(CC) || CC == CallingConv::AMDGPU_Gfx;
1329+
}
13131330

13141331
LLVM_READNONE
1315-
bool isCompute(CallingConv::ID CC);
1332+
constexpr bool isCompute(CallingConv::ID CC) {
1333+
return !isGraphics(CC) || CC == CallingConv::AMDGPU_CS;
1334+
}
13161335

13171336
LLVM_READNONE
1318-
bool isEntryFunctionCC(CallingConv::ID CC);
1337+
constexpr bool isEntryFunctionCC(CallingConv::ID CC) {
1338+
switch (CC) {
1339+
case CallingConv::AMDGPU_KERNEL:
1340+
case CallingConv::SPIR_KERNEL:
1341+
case CallingConv::AMDGPU_VS:
1342+
case CallingConv::AMDGPU_GS:
1343+
case CallingConv::AMDGPU_PS:
1344+
case CallingConv::AMDGPU_CS:
1345+
case CallingConv::AMDGPU_ES:
1346+
case CallingConv::AMDGPU_HS:
1347+
case CallingConv::AMDGPU_LS:
1348+
return true;
1349+
default:
1350+
return false;
1351+
}
1352+
}
1353+
1354+
LLVM_READNONE
1355+
constexpr bool isChainCC(CallingConv::ID CC) {
1356+
switch (CC) {
1357+
case CallingConv::AMDGPU_CS_Chain:
1358+
case CallingConv::AMDGPU_CS_ChainPreserve:
1359+
return true;
1360+
default:
1361+
return false;
1362+
}
1363+
}
13191364

13201365
// These functions are considered entrypoints into the current module, i.e. they
13211366
// are allowed to be called from outside the current module. This is different
@@ -1324,16 +1369,17 @@ bool isEntryFunctionCC(CallingConv::ID CC);
13241369
// include functions that can be called from other functions inside or outside
13251370
// the current module. Module entry functions are allowed to allocate LDS.
13261371
LLVM_READNONE
1327-
bool isModuleEntryFunctionCC(CallingConv::ID CC);
1328-
1329-
LLVM_READNONE
1330-
bool isChainCC(CallingConv::ID CC);
1331-
1332-
bool isKernelCC(const Function *Func);
1372+
constexpr bool isModuleEntryFunctionCC(CallingConv::ID CC) {
1373+
switch (CC) {
1374+
case CallingConv::AMDGPU_Gfx:
1375+
return true;
1376+
default:
1377+
return isEntryFunctionCC(CC) || isChainCC(CC);
1378+
}
1379+
}
13331380

1334-
// FIXME: Remove this when calling conventions cleaned up
13351381
LLVM_READNONE
1336-
inline bool isKernel(CallingConv::ID CC) {
1382+
constexpr inline bool isKernel(CallingConv::ID CC) {
13371383
switch (CC) {
13381384
case CallingConv::AMDGPU_KERNEL:
13391385
case CallingConv::SPIR_KERNEL:
@@ -1343,6 +1389,23 @@ inline bool isKernel(CallingConv::ID CC) {
13431389
}
13441390
}
13451391

1392+
LLVM_READNONE
1393+
constexpr bool canGuaranteeTCO(CallingConv::ID CC) {
1394+
return CC == CallingConv::Fast;
1395+
}
1396+
1397+
/// Return true if we might ever do TCO for calls with this calling convention.
1398+
LLVM_READNONE
1399+
constexpr bool mayTailCallThisCC(CallingConv::ID CC) {
1400+
switch (CC) {
1401+
case CallingConv::C:
1402+
case CallingConv::AMDGPU_Gfx:
1403+
return true;
1404+
default:
1405+
return canGuaranteeTCO(CC);
1406+
}
1407+
}
1408+
13461409
bool hasXNACK(const MCSubtargetInfo &STI);
13471410
bool hasSRAMECC(const MCSubtargetInfo &STI);
13481411
bool hasMIMG_R128(const MCSubtargetInfo &STI);

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