@@ -297,6 +297,12 @@ impl VectActive {
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mod scb_consts {
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pub const SCB_CCR_IC_MASK : u32 = ( 1 << 17 ) ;
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pub const SCB_CCR_DC_MASK : u32 = ( 1 << 16 ) ;
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+
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+ pub const SCB_ICSR_PENDSVSET_MASK : u32 = 1 << 28 ;
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+ pub const SCB_ICSR_PENDSVCLR_MASK : u32 = 1 << 27 ;
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+
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+ pub const SCB_ICSR_PENDSTSET_MASK : u32 = 1 << 26 ;
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+ pub const SCB_ICSR_PENDSTCLR_MASK : u32 = 1 << 25 ;
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}
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#[ cfg( not( armv6m) ) ]
@@ -576,6 +582,56 @@ impl SCB {
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:: asm:: dsb ( ) ;
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:: asm:: isb ( ) ;
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}
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+
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+ /// Pending SV Flag
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+ ///
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+ /// return true if PendSV exception is pending, otherwise false
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+ #[ inline]
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+ pub fn is_pendsv ( ) -> bool {
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+ // NOTE(unsafe) atomic read with no side effects
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+ unsafe { ( * Self :: ptr ( ) ) . icsr . read ( ) & SCB_ICSR_PENDSVSET_MASK != 0 }
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+ }
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+
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+ /// Changes PendSV exception state to pending Set Pending SV Flag
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+ #[ inline]
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+ pub fn set_pendsv ( & mut self ) {
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+ unsafe {
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+ self . icsr . write ( SCB_ICSR_PENDSVSET_MASK ) ;
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+ }
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+ }
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+
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+ /// Removes the pending state from the PendSV exception
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+ #[ inline]
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+ pub fn clear_pendsv ( & mut self ) {
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+ unsafe {
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+ self . icsr . write ( SCB_ICSR_PENDSVCLR_MASK ) ;
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+ }
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+ }
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+
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+ /// ICSR SysTick flag
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+ ///
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+ /// return true if SysTick exception is pending, otherwise false
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+ #[ inline]
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+ pub fn is_systick_pending ( ) -> bool {
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+ // NOTE(unsafe) atomic read with no side effects
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+ unsafe { ( * Self :: ptr ( ) ) . icsr . read ( ) & SCB_ICSR_PENDSTSET_MASK != 0 }
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+ }
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+
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+ /// Changes SysTick exception state to pending
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+ #[ inline]
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+ pub fn set_systick_pending ( & mut self ) {
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+ unsafe {
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+ self . icsr . write ( SCB_ICSR_PENDSTSET_MASK ) ;
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+ }
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+ }
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+
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+ /// Removes the pending state from the SysTick exception
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+ #[ inline]
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+ pub fn clear_systick_pending ( & mut self ) {
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+ unsafe {
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+ self . icsr . write ( SCB_ICSR_PENDSTCLR_MASK ) ;
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+ }
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+ }
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}
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const SCB_SCR_SLEEPDEEP : u32 = 0x1 << 2 ;
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