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1 parent ea7ce5c commit 4589661Copy full SHA for 4589661
src/peripheral/mod.rs
@@ -137,8 +137,9 @@ impl Cpuid {
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///
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/// * `level`: the required cache level minus 1, e.g. 0 for L1, 1 for L2
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/// * `ind`: select instruction cache or data/unified cache
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+ ///
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+ /// `level` is masked to be between 0 and 7.
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pub fn select_cache(&self, level: u8, ind: CsselrCacheType) {
- assert!(level<8);
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unsafe { self.csselr.write(
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(((level as u32) << CSSELR_LEVEL_POS) & CSSELR_LEVEL_MASK) |
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(((ind as u32) << CSSELR_IND_POS) & CSSELR_IND_MASK)
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