Auto merge of #76 - japaric:thumbv6m, r=japaric

hide ARMv7-M only peripherals on thumbv6m-none-eabi

None

Author: homunkulus

src/lib.rs

@@ -24,6 +24,8 @@ mod macros;
 pub mod asm;
 pub mod exception;
 pub mod interrupt;
+// NOTE(target_arch) is for documentation purposes
+#[cfg(any(armv7m, target_arch = "x86_64"))]
 pub mod itm;
 pub mod peripheral;
 pub mod register;

src/peripheral/cbp.rs

@@ -1,4 +1,6 @@
 //! Cache and branch predictor maintenance operations
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
 
 use volatile_register::WO;
 

src/peripheral/cpuid.rs

@@ -1,10 +1,10 @@
 //! CPUID
 
 use volatile_register::RO;
-#[cfg(any(armv7m, test))]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
 use volatile_register::RW;
 
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
 use peripheral::CPUID;
 
 /// Register block
@@ -25,29 +25,29 @@ pub struct RegisterBlock {
     pub isar: [RO<u32>; 5],
     reserved1: u32,
     /// Cache Level ID
-    #[cfg(any(armv7m, test))]
+    #[cfg(any(armv7m, target_arch = "x86_64"))]
     pub clidr: RO<u32>,
     /// Cache Type
-    #[cfg(any(armv7m, test))]
+    #[cfg(any(armv7m, target_arch = "x86_64"))]
     pub ctr: RO<u32>,
     /// Cache Size ID
-    #[cfg(any(armv7m, test))]
+    #[cfg(any(armv7m, target_arch = "x86_64"))]
     pub ccsidr: RO<u32>,
     /// Cache Size Selection
-    #[cfg(any(armv7m, test))]
+    #[cfg(any(armv7m, target_arch = "x86_64"))]
     pub csselr: RW<u32>,
 }
 
 /// Type of cache to select on CSSELR writes.
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
 pub enum CsselrCacheType {
     /// Select DCache or unified cache
     DataOrUnified = 0,
     /// Select ICache
     Instruction = 1,
 }
 
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
 impl CPUID {
     /// Selects the current CCSIDR
     ///

src/peripheral/fpb.rs

@@ -1,4 +1,6 @@
 //! Flash Patch and Breakpoint unit
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
 
 use volatile_register::{RO, RW, WO};
 

src/peripheral/fpu.rs

@@ -1,22 +1,19 @@
 //! Floating Point Unit
+//!
+//! *NOTE* Available only on ARMv7E-M (`thumbv7em-none-eabihf`)
 
-#[cfg(any(has_fpu, test))]
 use volatile_register::{RO, RW};
 
 /// Register block
 #[repr(C)]
 pub struct RegisterBlock {
     reserved: u32,
     /// Floating Point Context Control
-    #[cfg(any(has_fpu, test))]
     pub fpccr: RW<u32>,
     /// Floating Point Context Address
-    #[cfg(any(has_fpu, test))]
     pub fpcar: RW<u32>,
     /// Floating Point Default Status Control
-    #[cfg(any(has_fpu, test))]
     pub fpdscr: RW<u32>,
     /// Media and FP Feature
-    #[cfg(any(has_fpu, test))]
     pub mvfr: [RO<u32>; 3],
 }

src/peripheral/itm.rs

@@ -1,4 +1,6 @@
 //! Instrumentation Trace Macrocell
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
 
 use core::cell::UnsafeCell;
 use core::ptr;