Merge #527

527: add device.x  for riscv targets, and provides __EXTERNAL_INTERRUPTS r=therealprof a=allexoll

This PR is a proposal to address #526 . 

`__EXTERNAL_INTERRUPTS` is the symbol used since `__INTERRUPTS` is used by [riscv-rt](https://github.com/rust-embedded/riscv-rt/blob/47ece5f5163a2e38ce5e4685b5d3145713d7954a/src/lib.rs#L505)

I think it fits because the peripheral interrupts are supposed to be pending through the external interrupt. 

This provides hals with information to manage interrupt request. either through a PLIC or trough the vectored interrupt when that is implemented (in [riscv-rt](https://github.com/rust-embedded/riscv-rt/issues/1) i suppose).

Remarks welcome

Co-authored-by: Alexis Marquet <[email protected]>

Author: bors[bot]

CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Support for device.x generation for riscv targets and `__EXTERNAL_INTERRUPTS` vector table
+
 ## [v0.19.0] - 2021-05-26
 
 ### Added

src/generate/interrupt.rs

@@ -125,7 +125,31 @@ pub fn render(
                     ];
             });
         }
-        Target::RISCV => {}
+        Target::RISCV => {
+            for name in &names {
+                writeln!(device_x, "PROVIDE({} = DefaultHandler);", name)?;
+            }
+
+            root.extend(quote! {
+                #[cfg(feature = "rt")]
+                extern "C" {
+                    #(fn #names();)*
+                }
+
+                #[doc(hidden)]
+                pub union Vector {
+                    pub _handler: unsafe extern "C" fn(),
+                    pub _reserved: usize,
+                }
+
+                #[cfg(feature = "rt")]
+                #[doc(hidden)]
+                #[no_mangle]
+                pub static __EXTERNAL_INTERRUPTS: [Vector; #n] = [
+                    #elements
+                ];
+            });
+        }
         Target::XtensaLX => {
             for name in &names {
                 writeln!(device_x, "PROVIDE({} = DefaultHandler);", name)?;

src/main.rs

@@ -160,7 +160,11 @@ fn run() -> Result<()> {
     file.write_all(data.as_ref())
         .expect("Could not write code to lib.rs");
 
-    if target == Target::CortexM || target == Target::Msp430 || target == Target::XtensaLX {
+    if target == Target::CortexM
+        || target == Target::Msp430
+        || target == Target::XtensaLX
+        || target == Target::RISCV
+    {
         writeln!(File::create(path.join("device.x"))?, "{}", device_x)?;
         writeln!(File::create(path.join("build.rs"))?, "{}", build_rs())?;
     }