Skip to content

Commit b27c5a5

Browse files
bors[bot]Disasm
andcommitted
Merge #295
295: Add support for 64-bit registers r=therealprof a=Disasm Some registers on K210 chip are 64-bit, so it's better to declare them as u64 in SVD for the reasons mentioned here: riscv-rust/k210-pac#1 (comment) At the moment, svd2rust forbids 64-bit register declarations. This PR fixes this. This change can cause silent bugs on platforms without 64-bit memory access operations due to the need for proper access sequence to 64-bit registers with two 32-bit accesses. Closes #289 Co-authored-by: Vadim Kaushan <[email protected]>
2 parents 3073d7e + 6dc10b8 commit b27c5a5

File tree

2 files changed

+20
-4
lines changed

2 files changed

+20
-4
lines changed

ci/script.sh

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -427,9 +427,12 @@ main() {
427427
cd $td &&
428428
curl -LO \
429429
https://github.com/pftbest/msp430g2553/raw/v0.1.0/msp430g2553.svd
430-
cd $td &&
431-
curl -LO \
432-
https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x.svd
430+
cd $td &&
431+
curl -LO \
432+
https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x.svd
433+
cd $td &&
434+
curl -LO \
435+
https://raw.githubusercontent.com/riscv-rust/k210-pac/master/k210.svd
433436
)
434437

435438
local cwd=$(pwd)
@@ -445,7 +448,7 @@ main() {
445448

446449
cargo check --manifest-path $td/Cargo.toml
447450

448-
# Test RISC-V
451+
# Test RISC-V FE310
449452
pushd $td
450453

451454
$cwd/target/$TARGET/release/svd2rust --target riscv -i $td/e310x.svd
@@ -455,6 +458,17 @@ main() {
455458
popd
456459

457460
cargo check --manifest-path $td/Cargo.toml
461+
462+
# Test RISC-V K210
463+
pushd $td
464+
465+
RUST_BACKTRACE=1 $cwd/target/$TARGET/release/svd2rust --target riscv -i $td/k210.svd
466+
mv $td/lib.rs $td/src/lib.rs
467+
rustfmt $td/src/lib.rs || true
468+
469+
popd
470+
471+
cargo check --manifest-path $td/Cargo.toml
458472
;;
459473

460474
Nordic)

src/util.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -267,6 +267,7 @@ impl U32Ext for u32 {
267267
2...8 => Ident::new("u8"),
268268
9...16 => Ident::new("u16"),
269269
17...32 => Ident::new("u32"),
270+
33...64 => Ident::new("u64"),
270271
_ => Err(format!(
271272
"can't convert {} bits into a Rust integral type",
272273
*self
@@ -280,6 +281,7 @@ impl U32Ext for u32 {
280281
2...8 => 8,
281282
9...16 => 16,
282283
17...32 => 32,
284+
33...64 => 64,
283285
_ => Err(format!(
284286
"can't convert {} bits into a Rust integral type width",
285287
*self

0 commit comments

Comments
 (0)