[DAG] Move SelectionDAG implementation to KnownBits::setInReg(). NFCI.

Author: RKSimon

llvm/include/llvm/Support/KnownBits.h

@@ -179,6 +179,10 @@ struct KnownBits {
     return *this;
   }
 
+  /// Return known bits for a in-register sign extension of the value we're
+  /// tracking.
+  KnownBits sextInReg(unsigned SrcBitWidth) const;
+
   /// Return a KnownBits with the extracted bits
   /// [bitPosition,bitPosition+numBits).
   KnownBits extractBits(unsigned NumBits, unsigned BitPosition) const {

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -2999,38 +2999,9 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
     }
     break;
   case ISD::SIGN_EXTEND_INREG: {
-    EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
-    unsigned EBits = EVT.getScalarSizeInBits();
-
-    // Sign extension.  Compute the demanded bits in the result that are not
-    // present in the input.
-    APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits);
-
-    APInt InSignMask = APInt::getSignMask(EBits);
-    APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, EBits);
-
-    // If the sign extended bits are demanded, we know that the sign
-    // bit is demanded.
-    InSignMask = InSignMask.zext(BitWidth);
-    if (NewBits.getBoolValue())
-      InputDemandedBits |= InSignMask;
-
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
-    Known.One &= InputDemandedBits;
-    Known.Zero &= InputDemandedBits;
-
-    // If the sign bit of the input is known set or clear, then we know the
-    // top bits of the result.
-    if (Known.Zero.intersects(InSignMask)) {        // Input sign bit known clear
-      Known.Zero |= NewBits;
-      Known.One  &= ~NewBits;
-    } else if (Known.One.intersects(InSignMask)) {  // Input sign bit known set
-      Known.One  |= NewBits;
-      Known.Zero &= ~NewBits;
-    } else {                              // Input sign bit unknown
-      Known.Zero &= ~NewBits;
-      Known.One  &= ~NewBits;
-    }
+    EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+    Known = Known.sextInReg(EVT.getScalarSizeInBits());
     break;
   }
   case ISD::CTTZ:

llvm/lib/Support/KnownBits.cpp

@@ -83,6 +83,41 @@ KnownBits KnownBits::computeForAddSub(bool Add, bool NSW,
   return KnownOut;
 }
 
+KnownBits KnownBits::sextInReg(unsigned SrcBitWidth) const {
+  unsigned BitWidth = getBitWidth();
+  assert(BitWidth >= SrcBitWidth && "Illegal sext-in-register");
+
+  // Sign extension.  Compute the demanded bits in the result that are not
+  // present in the input.
+  APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth);
+
+  // If the sign extended bits are demanded, we know that the sign
+  // bit is demanded.
+  APInt InSignMask = APInt::getSignMask(SrcBitWidth).zext(BitWidth);
+  APInt InDemandedBits = APInt::getLowBitsSet(BitWidth, SrcBitWidth);
+  if (NewBits.getBoolValue())
+    InDemandedBits |= InSignMask;
+
+  KnownBits Result;
+  Result.One = One & InDemandedBits;
+  Result.Zero = Zero & InDemandedBits;
+
+  // If the sign bit of the input is known set or clear, then we know the
+  // top bits of the result.
+  if (Result.Zero.intersects(InSignMask)) { // Input sign bit known clear
+    Result.Zero |= NewBits;
+    Result.One &= ~NewBits;
+  } else if (Result.One.intersects(InSignMask)) { // Input sign bit known set
+    Result.One |= NewBits;
+    Result.Zero &= ~NewBits;
+  } else { // Input sign bit unknown
+    Result.Zero &= ~NewBits;
+    Result.One &= ~NewBits;
+  }
+
+  return Result;
+}
+
 KnownBits KnownBits::makeGE(const APInt &Val) const {
   // Count the number of leading bit positions where our underlying value is
   // known to be less than or equal to Val.