Skip to content
This repository was archived by the owner on May 28, 2025. It is now read-only.

Commit e8f1c5c

Browse files
committed
Don't forbid i64x2 as simd type
1 parent 67028ce commit e8f1c5c

File tree

1 file changed

+2
-4
lines changed

1 file changed

+2
-4
lines changed

src/intrinsics/mod.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -182,10 +182,8 @@ pub(crate) fn clif_vector_type<'tcx>(tcx: TyCtxt<'tcx>, layout: TyAndLayout<'tcx
182182
};
183183

184184
match scalar_to_clif_type(tcx, element).by(u16::try_from(count).unwrap()) {
185-
// Cranelift currently only implements icmp for 128bit vectors. While 64bit lanes are
186-
// supported, this needs either the `use_sse41_simd` or `use_sse42_simd` target flag
187-
// to be enabled.
188-
Some(vector_ty) if vector_ty.bits() == 128 && vector_ty.lane_type() != types::I64 => Some(vector_ty),
185+
// Cranelift currently only implements icmp for 128bit vectors.
186+
Some(vector_ty) if vector_ty.bits() == 128 => Some(vector_ty),
189187
_ => None,
190188
}
191189
}

0 commit comments

Comments
 (0)