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Pre-commit test cases missing SSHLSAT/USHLSAT folds. NFC
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‎llvm/test/CodeGen/AArch64/sshl_sat.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i16 @llvm.sshl.sat.i16(i16, i16)
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declare <4 x i16> @llvm.sshl.sat.v4i16(<4 x i16>, <4 x i16>)
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; fold (shlsat undef, x) -> 0
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define i16 @combine_shl_undef(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: mov w9, #-2147483648
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: csel w8, w9, w8, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 undef, i16 %y)
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ret i16 %tmp
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}
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; fold (shlsat x, undef) -> undef
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define i16 @combine_shl_by_undef(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_by_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w9, w0, #16
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; CHECK-NEXT: mov w8, #-2147483648
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; CHECK-NEXT: cmp w9, #0
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; CHECK-NEXT: cinv w8, w8, ge
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; CHECK-NEXT: cmp w9, w9
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; CHECK-NEXT: csel w8, w8, w9, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 undef)
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ret i16 %tmp
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}
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; fold (shlsat poison, x) -> 0
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define i16 @combine_shl_poison(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: mov w9, #-2147483648
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: csel w8, w9, w8, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 poison, i16 %y)
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ret i16 %tmp
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}
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; fold (shlsat x, poison) -> undef
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define i16 @combine_shl_by_poison(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_by_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w9, w0, #16
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; CHECK-NEXT: mov w8, #-2147483648
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; CHECK-NEXT: cmp w9, #0
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; CHECK-NEXT: cinv w8, w8, ge
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; CHECK-NEXT: cmp w9, w9
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; CHECK-NEXT: csel w8, w8, w9, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 poison)
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ret i16 %tmp
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}
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; fold (shlsat x, bitwidth) -> undef
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define i16 @combine_shl_by_bitwidth(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w9, w0, #16
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; CHECK-NEXT: mov w8, #-2147483648
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; CHECK-NEXT: cmp w9, #0
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; CHECK-NEXT: cinv w8, w8, ge
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; CHECK-NEXT: csel w8, w8, wzr, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 16)
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ret i16 %tmp
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}
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; fold (shlsat 0, x) -> 0
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define i16 @combine_shl_zero(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: mov w9, #-2147483648
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: csel w8, w9, w8, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 0, i16 %y)
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ret i16 %tmp
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}
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; fold (shlsat x, 0) -> x
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define i16 @combine_shlsat_by_zero(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_by_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w9, w0, #16
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; CHECK-NEXT: mov w8, #-2147483648
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; CHECK-NEXT: cmp w9, #0
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; CHECK-NEXT: cinv w8, w8, ge
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; CHECK-NEXT: cmp w9, w9
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; CHECK-NEXT: csel w8, w8, w9, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 0)
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ret i16 %tmp
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}
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; fold (shlsat c1, c2) -> c3
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define i16 @combine_shlsat_constfold(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_constfold:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #524288
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; CHECK-NEXT: mov w9, #-2147483648
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: cmp w8, #128, lsl #12 // =524288
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; CHECK-NEXT: mov w8, #2097152
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; CHECK-NEXT: csel w8, w9, w8, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 8, i16 2)
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ret i16 %tmp
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}
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; fold (shlsat c1, c2) -> sat max
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define i16 @combine_shlsat_satmax(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_satmax:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #524288
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: mov w8, #-2147483648
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; CHECK-NEXT: cinv w8, w8, ge
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; CHECK-NEXT: csel w8, w8, wzr, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 8, i16 15)
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ret i16 %tmp
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}
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; fold (shlsat c1, c2) -> sat min
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define i16 @combine_shlsat_satmin(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_satmin:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-524288
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: mov w8, #-2147483648
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; CHECK-NEXT: cinv w8, w8, ge
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; CHECK-NEXT: csel w8, w8, wzr, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 -8, i16 15)
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ret i16 %tmp
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}
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declare void @sink4xi16(i16, i16, i16, i16)
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; fold (shlsat c1, c2) -> c3 , c1/c2/c3 being vectors
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define void @combine_shlsat_vector() nounwind {
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; CHECK-LABEL: combine_shlsat_vector:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: mov w8, #524288
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; CHECK-NEXT: mov w9, #-2147483648
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cinv w10, w9, ge
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; CHECK-NEXT: csel w11, w10, wzr, ne
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; CHECK-NEXT: cmp w8, #128, lsl #12 // =524288
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; CHECK-NEXT: mov w8, #2097152
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; CHECK-NEXT: asr w11, w11, #16
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; CHECK-NEXT: csel w8, w10, w8, ne
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; CHECK-NEXT: mov w10, #-524288
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; CHECK-NEXT: asr w8, w8, #16
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; CHECK-NEXT: cmp w10, #0
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; CHECK-NEXT: cinv w9, w9, ge
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: csel w8, w9, wzr, ne
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; CHECK-NEXT: cmn w10, #128, lsl #12 // =524288
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; CHECK-NEXT: mov w10, #-2097152
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; CHECK-NEXT: csel w9, w9, w10, ne
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; CHECK-NEXT: asr w8, w8, #16
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; CHECK-NEXT: mov v0.h[1], w11
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; CHECK-NEXT: asr w9, w9, #16
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; CHECK-NEXT: mov v0.h[2], w9
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; CHECK-NEXT: mov v0.h[3], w8
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; CHECK-NEXT: umov w0, v0.h[0]
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; CHECK-NEXT: umov w1, v0.h[1]
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; CHECK-NEXT: umov w2, v0.h[2]
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; CHECK-NEXT: umov w3, v0.h[3]
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; CHECK-NEXT: bl sink4xi16
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; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%tmp = call <4 x i16> @llvm.sshl.sat.v4i16(
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<4 x i16><i16 8, i16 8, i16 -8, i16 -8>,
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<4 x i16><i16 2, i16 15, i16 2, i16 15>)
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; Pass elements as arguments in a call to get CHECK statements that verify
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; the constant folding.
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%e0 = extractelement <4 x i16> %tmp, i16 0
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%e1 = extractelement <4 x i16> %tmp, i16 1
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%e2 = extractelement <4 x i16> %tmp, i16 2
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%e3 = extractelement <4 x i16> %tmp, i16 3
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call void @sink4xi16(i16 %e0, i16 %e1, i16 %e2, i16 %e3)
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ret void
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}

‎llvm/test/CodeGen/AArch64/ushl_sat.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i16 @llvm.ushl.sat.i16(i16, i16)
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declare <2 x i16> @llvm.ushl.sat.v2i16(<2 x i16>, <2 x i16>)
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; fold (shlsat undef, x) -> 0
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define i16 @combine_shl_undef(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ushl.sat.i16(i16 undef, i16 %y)
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ret i16 %tmp
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}
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; fold (shlsat x, undef) -> undef
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define i16 @combine_shl_by_undef(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_by_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: cmp w8, w8
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; CHECK-NEXT: csinv w8, w8, wzr, eq
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ushl.sat.i16(i16 %x, i16 undef)
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ret i16 %tmp
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}
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; fold (shlsat poison, x) -> 0
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define i16 @combine_shl_poison(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ushl.sat.i16(i16 poison, i16 %y)
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ret i16 %tmp
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}
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; fold (shlsat x, poison) -> undef
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define i16 @combine_shl_by_poison(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_by_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: cmp w8, w8
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; CHECK-NEXT: csinv w8, w8, wzr, eq
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ushl.sat.i16(i16 %x, i16 poison)
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ret i16 %tmp
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}
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; fold (shlsat x, bitwidth) -> undef
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define i16 @combine_shl_by_bitwidth(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ushl.sat.i16(i16 %x, i16 16)
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ret i16 %tmp
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}
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; fold (ushlsat 0, x) -> 0
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define i16 @combine_shl_zero(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ushl.sat.i16(i16 0, i16 %y)
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ret i16 %tmp
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}
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; fold (ushlsat x, 0) -> x
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define i16 @combine_shlsat_by_zero(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_by_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: cmp w8, w8
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; CHECK-NEXT: csinv w8, w8, wzr, eq
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ushl.sat.i16(i16 %x, i16 0)
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ret i16 %tmp
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}
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; fold (ushlsat c1, c2) -> c3
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define i16 @combine_shlsat_constfold(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_constfold:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #524288
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; CHECK-NEXT: cmp w8, #128, lsl #12 // =524288
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; CHECK-NEXT: mov w8, #2097152
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; CHECK-NEXT: csinv w8, w8, wzr, eq
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ushl.sat.i16(i16 8, i16 2)
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ret i16 %tmp
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}
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; fold (ushlsat c1, c2) -> sat max
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define i16 @combine_shlsat_satmax(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_satmax:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #524288
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ushl.sat.i16(i16 8, i16 15)
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ret i16 %tmp
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}
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declare void @sink2xi16(i16, i16)
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; fold (ushlsat c1, c2) -> c3 , c1/c2/c3 being vectors
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define void @combine_shlsat_vector() nounwind {
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; CHECK-LABEL: combine_shlsat_vector:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: mov w8, #524288
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; CHECK-NEXT: mov w9, #2097152
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; CHECK-NEXT: cmp w8, #128, lsl #12 // =524288
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; CHECK-NEXT: csinv w9, w9, wzr, eq
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: fmov s0, w9
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; CHECK-NEXT: mov v0.s[1], w8
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; CHECK-NEXT: ushr v0.2s, v0.2s, #16
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; CHECK-NEXT: mov w1, v0.s[1]
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: bl sink2xi16
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; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%tmp = call <2 x i16> @llvm.ushl.sat.v2i16(<2 x i16><i16 8, i16 8>,
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<2 x i16><i16 2, i16 15>)
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; Pass elements as arguments in a call to get CHECK statements that verify
150+
; the constant folding.
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%e0 = extractelement <2 x i16> %tmp, i16 0
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%e1 = extractelement <2 x i16> %tmp, i16 1
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call void @sink2xi16(i16 %e0, i16 %e1)
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ret void
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}

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