We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 71e8021 commit 0cfdce2Copy full SHA for 0cfdce2
llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
@@ -98,6 +98,7 @@ static_library("LLVMX86CodeGen") {
98
"X86ISelDAGToDAG.cpp",
99
"X86ISelLowering.cpp",
100
"X86IndirectBranchTracking.cpp",
101
+ "X86IndirectThunks.cpp",
102
"X86InsertPrefetch.cpp",
103
"X86InsertWait.cpp",
104
"X86InstrFMA3Info.cpp",
@@ -114,7 +115,6 @@ static_library("LLVMX86CodeGen") {
114
115
"X86PartialReduction.cpp",
116
"X86RegisterBankInfo.cpp",
117
"X86RegisterInfo.cpp",
- "X86RetpolineThunks.cpp",
118
"X86SelectionDAGInfo.cpp",
119
"X86ShuffleDecodeConstantPool.cpp",
120
"X86SpeculativeLoadHardening.cpp",
0 commit comments