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Jessica Paquette
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[AArch64][GlobalISel] Clamp vectors of p0 when legalizing G_LOAD/G_STORE
We had a rule for <n x s64> but not one for <n x p0>. As a result, we'd fall back on like <5 x p0> or whatever. Differential Revision: https://reviews.llvm.org/D108484
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+62
-11
lines changed

3 files changed

+62
-11
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -307,6 +307,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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.clampMaxNumElements(0, s16, 8)
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.clampMaxNumElements(0, s32, 4)
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.clampMaxNumElements(0, s64, 2)
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.clampMaxNumElements(0, p0, 2)
310311
.customIf(IsPtrVecPred)
311312
.scalarizeIf(typeIs(0, v2s16), 0);
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@@ -342,6 +343,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
342343
.clampMaxNumElements(0, s16, 8)
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.clampMaxNumElements(0, s32, 4)
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.clampMaxNumElements(0, s64, 2)
346+
.clampMaxNumElements(0, p0, 2)
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.lowerIfMemSizeNotPow2()
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.customIf(IsPtrVecPred)
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.scalarizeIf(typeIs(0, v2s16), 0);

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -674,3 +674,47 @@ body: |
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%ext:_(s64) = G_ZEXT %load
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$x0 = COPY %ext
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RET_ReallyLR implicit $x0
677+
...
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---
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name: load_store_6xp0
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alignment: 4
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: load_store_6xp0
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; CHECK: liveins: $x0
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; CHECK: %ptr:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD %ptr(p0) :: (load (p0), align 64)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
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; CHECK: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD]](p0) :: (load (p0) from unknown-address + 8)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
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; CHECK: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD1]](p0) :: (load (p0) from unknown-address + 16, align 16)
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
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; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C2]](s64)
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; CHECK: [[LOAD3:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD2]](p0) :: (load (p0) from unknown-address + 24)
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; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
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; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C3]](s64)
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; CHECK: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD3]](p0) :: (load (p0) from unknown-address + 32, align 32)
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; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
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; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C4]](s64)
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; CHECK: [[LOAD5:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD4]](p0) :: (load (p0) from unknown-address + 40)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[LOAD]](p0), [[LOAD1]](p0)
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[LOAD2]](p0), [[LOAD3]](p0)
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; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[LOAD4]](p0), [[LOAD5]](p0)
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; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BUILD_VECTOR]](<2 x p0>)
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; CHECK: G_STORE [[BITCAST]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 64)
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; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
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; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BUILD_VECTOR1]](<2 x p0>)
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; CHECK: G_STORE [[BITCAST1]](<2 x s64>), [[PTR_ADD5]](p0) :: (store (<2 x s64>) into unknown-address + 16)
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; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C3]](s64)
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; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BUILD_VECTOR2]](<2 x p0>)
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; CHECK: G_STORE [[BITCAST2]](<2 x s64>), [[PTR_ADD6]](p0) :: (store (<2 x s64>) into unknown-address + 32, align 32)
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; CHECK: RET_ReallyLR
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%ptr:_(p0) = COPY $x0
718+
%val:_(<6 x p0>) = G_LOAD %ptr(p0) :: (load (<6 x p0>))
719+
G_STORE %val(<6 x p0>), %ptr(p0) :: (store (<6 x p0>))
720+
RET_ReallyLR

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir

Lines changed: 16 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -854,22 +854,27 @@ body: |
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; CHECK: %ptr1:_(p0) = COPY $x1
855855
; CHECK: %ptr2:_(p0) = COPY $x0
856856
; CHECK: %cond:_(s1) = G_IMPLICIT_DEF
857-
; CHECK: %val_1:_(<4 x p0>) = G_LOAD %ptr1(p0) :: (load (<4 x p0>))
858-
; CHECK: [[UV:%[0-9]+]]:_(<2 x p0>), [[UV1:%[0-9]+]]:_(<2 x p0>) = G_UNMERGE_VALUES %val_1(<4 x p0>)
857+
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
858+
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
859+
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
860+
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr1, [[C]](s64)
861+
; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
862+
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
859863
; CHECK: G_BRCOND %cond(s1), %bb.2
860864
; CHECK: G_BR %bb.1
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; CHECK: bb.1:
862866
; CHECK: successors: %bb.2(0x80000000)
863-
; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD %ptr2(p0) :: (load (<4 x s64>))
864-
; CHECK: %val_2:_(<4 x p0>) = G_BITCAST [[LOAD]](<4 x s64>)
865-
; CHECK: [[UV2:%[0-9]+]]:_(<2 x p0>), [[UV3:%[0-9]+]]:_(<2 x p0>) = G_UNMERGE_VALUES %val_2(<4 x p0>)
867+
; CHECK: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
868+
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
869+
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
870+
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr2, [[C1]](s64)
871+
; CHECK: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
872+
; CHECK: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD3]](<2 x s64>)
866873
; CHECK: bb.2:
867-
; CHECK: [[PHI:%[0-9]+]]:_(<2 x p0>) = G_PHI [[UV2]](<2 x p0>), %bb.1, [[UV]](<2 x p0>), %bb.0
868-
; CHECK: [[PHI1:%[0-9]+]]:_(<2 x p0>) = G_PHI [[UV3]](<2 x p0>), %bb.1, [[UV1]](<2 x p0>), %bb.0
869-
; CHECK: %phi:_(<4 x p0>) = G_CONCAT_VECTORS [[PHI]](<2 x p0>), [[PHI1]](<2 x p0>)
870-
; CHECK: %unmerge_1:_(<2 x p0>), %unmerge_2:_(<2 x p0>) = G_UNMERGE_VALUES %phi(<4 x p0>)
871-
; CHECK: $q0 = COPY %unmerge_1(<2 x p0>)
872-
; CHECK: $q1 = COPY %unmerge_2(<2 x p0>)
874+
; CHECK: [[PHI:%[0-9]+]]:_(<2 x p0>) = G_PHI [[BITCAST2]](<2 x p0>), %bb.1, [[BITCAST]](<2 x p0>), %bb.0
875+
; CHECK: [[PHI1:%[0-9]+]]:_(<2 x p0>) = G_PHI [[BITCAST3]](<2 x p0>), %bb.1, [[BITCAST1]](<2 x p0>), %bb.0
876+
; CHECK: $q0 = COPY [[PHI]](<2 x p0>)
877+
; CHECK: $q1 = COPY [[PHI1]](<2 x p0>)
873878
; CHECK: RET_ReallyLR implicit $q0, implicit $q1
874879
bb.0:
875880
successors: %bb.1(0x50000000), %bb.2(0x30000000)

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