[GISEL][RISCV] RegBank Select for Scalable Vector Load/Store (llvm#99932)

This patch supports GlobalISel for register bank selection for scalable vector
load and store instructions in RISC-V

Author: jiahanxie353

llvm/lib/CodeGen/RegisterBankInfo.cpp

@@ -215,8 +215,9 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
       }
     }
 
-    unsigned Size = getSizeInBits(Reg, MRI, TRI);
-    const ValueMapping *ValMapping = &getValueMapping(0, Size, *CurRegBank);
+    TypeSize Size = getSizeInBits(Reg, MRI, TRI);
+    const ValueMapping *ValMapping =
+        &getValueMapping(0, Size.getKnownMinValue(), *CurRegBank);
     if (IsCopyLike) {
       if (!OperandsMapping[0]) {
         if (MI.isRegSequence()) {

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

@@ -310,10 +310,18 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   switch (Opc) {
   case TargetOpcode::G_LOAD: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
-    OpdsMapping[0] = GPRValueMapping;
+    TypeSize Size = Ty.getSizeInBits();
+    if (Ty.isVector())
+      OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
+    else
+      OpdsMapping[0] = GPRValueMapping;
+
     OpdsMapping[1] = GPRValueMapping;
+
+    if (Ty.isVector())
+      break;
     // Use FPR64 for s64 loads on rv32.
-    if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
+    if (GPRSize == 32 && Size.getFixedValue() == 64) {
       assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
       OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
       break;
@@ -333,10 +341,19 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   }
   case TargetOpcode::G_STORE: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
-    OpdsMapping[0] = GPRValueMapping;
+    TypeSize Size = Ty.getSizeInBits();
+    if (Ty.isVector())
+      OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
+    else
+      OpdsMapping[0] = GPRValueMapping;
+
     OpdsMapping[1] = GPRValueMapping;
+
+    if (Ty.isVector())
+      break;
+
     // Use FPR64 for s64 stores on rv32.
-    if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
+    if (GPRSize == 32 && Size.getFixedValue() == 64) {
       assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
       OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
       break;