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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | +; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s |
| 3 | +; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv3_sf,+fpuv3_df -float-abi=hard | FileCheck %s --check-prefix=CHECK-DF3 |
| 4 | +; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC |
| 5 | + |
| 6 | +define float @selectRR_eq_float(i1 %x, float %n, float %m) { |
| 7 | +; CHECK-LABEL: selectRR_eq_float: |
| 8 | +; CHECK: # %bb.0: # %entry |
| 9 | +; CHECK-NEXT: btsti32 a0, 0 |
| 10 | +; CHECK-NEXT: bt32 .LBB0_2 |
| 11 | +; CHECK-NEXT: # %bb.1: # %entry |
| 12 | +; CHECK-NEXT: fmovs vr1, vr0 |
| 13 | +; CHECK-NEXT: .LBB0_2: # %entry |
| 14 | +; CHECK-NEXT: fmovs vr0, vr1 |
| 15 | +; CHECK-NEXT: rts16 |
| 16 | +; |
| 17 | +; CHECK-DF3-LABEL: selectRR_eq_float: |
| 18 | +; CHECK-DF3: # %bb.0: # %entry |
| 19 | +; CHECK-DF3-NEXT: btsti32 a0, 0 |
| 20 | +; CHECK-DF3-NEXT: fsel.32 vr0, vr1, vr0 |
| 21 | +; CHECK-DF3-NEXT: rts16 |
| 22 | +; |
| 23 | +; GENERIC-LABEL: selectRR_eq_float: |
| 24 | +; GENERIC: # %bb.0: # %entry |
| 25 | +; GENERIC-NEXT: .cfi_def_cfa_offset 0 |
| 26 | +; GENERIC-NEXT: subi16 sp, sp, 4 |
| 27 | +; GENERIC-NEXT: .cfi_def_cfa_offset 4 |
| 28 | +; GENERIC-NEXT: btsti16 a0, 0 |
| 29 | +; GENERIC-NEXT: bt16 .LBB0_2 |
| 30 | +; GENERIC-NEXT: # %bb.1: # %entry |
| 31 | +; GENERIC-NEXT: fmovs vr1, vr0 |
| 32 | +; GENERIC-NEXT: .LBB0_2: # %entry |
| 33 | +; GENERIC-NEXT: fmovs vr0, vr1 |
| 34 | +; GENERIC-NEXT: addi16 sp, sp, 4 |
| 35 | +; GENERIC-NEXT: rts16 |
| 36 | +entry: |
| 37 | + %ret = select i1 %x, float %m, float %n |
| 38 | + ret float %ret |
| 39 | +} |
| 40 | + |
| 41 | +define double @selectRR_eq_double(i1 %x, double %n, double %m) { |
| 42 | +; CHECK-LABEL: selectRR_eq_double: |
| 43 | +; CHECK: # %bb.0: # %entry |
| 44 | +; CHECK-NEXT: btsti32 a0, 0 |
| 45 | +; CHECK-NEXT: bt32 .LBB1_2 |
| 46 | +; CHECK-NEXT: # %bb.1: # %entry |
| 47 | +; CHECK-NEXT: fmovd vr1, vr0 |
| 48 | +; CHECK-NEXT: .LBB1_2: # %entry |
| 49 | +; CHECK-NEXT: fmovd vr0, vr1 |
| 50 | +; CHECK-NEXT: rts16 |
| 51 | +; |
| 52 | +; CHECK-DF3-LABEL: selectRR_eq_double: |
| 53 | +; CHECK-DF3: # %bb.0: # %entry |
| 54 | +; CHECK-DF3-NEXT: btsti32 a0, 0 |
| 55 | +; CHECK-DF3-NEXT: fsel.64 vr0, vr1, vr0 |
| 56 | +; CHECK-DF3-NEXT: rts16 |
| 57 | +; |
| 58 | +; GENERIC-LABEL: selectRR_eq_double: |
| 59 | +; GENERIC: # %bb.0: # %entry |
| 60 | +; GENERIC-NEXT: .cfi_def_cfa_offset 0 |
| 61 | +; GENERIC-NEXT: subi16 sp, sp, 4 |
| 62 | +; GENERIC-NEXT: .cfi_def_cfa_offset 4 |
| 63 | +; GENERIC-NEXT: btsti16 a0, 0 |
| 64 | +; GENERIC-NEXT: bt16 .LBB1_2 |
| 65 | +; GENERIC-NEXT: # %bb.1: # %entry |
| 66 | +; GENERIC-NEXT: fmovd vr1, vr0 |
| 67 | +; GENERIC-NEXT: .LBB1_2: # %entry |
| 68 | +; GENERIC-NEXT: fmovd vr0, vr1 |
| 69 | +; GENERIC-NEXT: addi16 sp, sp, 4 |
| 70 | +; GENERIC-NEXT: rts16 |
| 71 | +entry: |
| 72 | + %ret = select i1 %x, double %m, double %n |
| 73 | + ret double %ret |
| 74 | +} |
| 75 | + |
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